33894 datasheet(16/28 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33894

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33894 is one in a family of devices designed for low-

voltage automotive and industrial lighting and motor control

applications. Its four low RDS(ON) MOSFETs (four 35 mΩ)

can control the high sides of four separate resistive or

inductive loads.

Programming, control, and diagnostics are accomplished

using a 16-bit SPI interface. Additionally, each output has its

own parallel input for PWM control if desired. The 33894

allows the user to program via the SPI the fault current trip

levels and duration of acceptable lamp inrush or motor stall

intervals. Such programmability allows tight control of fault

currents and can protect wiring harnesses and circuit boards

as well as loads.

The 33894 is packaged in a power-enhanced 12 x 12

nonleaded PQFN package with exposed tabs.

FUNCTIONAL PIN DESCRIPTION

SPI PROTOCOL DESCRIPTION

The SPI interface has a full duplex, three-wire

synchronous data transfer with four I/O lines associated with

it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),

and Chip Select (CS).

The SI/SO pins of the 33894 follow a first-in first-out (D15

to D0) protocol, with both input and output words transferring

the most significant bit (MSB) first. All inputs are compatible

with 5.0 V CMOS logic levels.

The SPI lines perform the following functions:

SERIAL INPUT (SI)

This is a serial interface (SI) command data input pin.

Each SI bit is read on the falling edge of SCLK. A 16-bit

stream of serial data is required on the SI pin, starting with

D15 to D0. The internal registers of the 33894 are configured

and controlled using a 5-bit addressing scheme described in

Table 7, page 19. Register addressing and configuration are

described in Table 8, page 20. The SI input has an active

internal pulldown, IDWN.

SERIAL OUTPUT (SO)

The SO data pin is a tri-stateable output from the shift

the CS pin is put into a logic [0] state. The SO data is capable

of reporting the status of the output, the device configuration,

and the state of the key inputs. The SO pin changes state on

the rising edge of SCLK and reads out on the falling edge of

SCLK. Fault and input status descriptions are provided in

Table 15, page 23.

SERIAL CLOCK (SCLK)

The SCLK pin clocks the internal shift registers of the

33894 device. The serial input (SI) pin accepts data into the

input shift register on the falling edge of the SCLK signal

while the serial output (SO) pin shifts data information out of

the SO line driver on the rising edge of the SCLK signal. It is

important the SCLK pin be in a logic low state whenever CS

makes any transition. For this reason, it is recommended the

SCLK pin be in logic [0] whenever the device is not accessed

(CS logic [1] state). SCLK has an active internal pulldown.

When CS is logic [1], signals at the SCLK and SI pins are

ignored and SO is tri-stated (high impedance) (see Figure 9,

page 19).

CHIP SELECT (CS)

The CS pin enables communication with the master

microcontroller (MCU). When this pin is in a logic [0] state,

the device is capable of transferring information to, and

receiving information from, the MCU. The 33894 latches in

data from the input shift registers to the addressed registers

on the rising edge of CS. The device transfers status

information from the power output to the Shift register on the

falling edge of CS. The SO output driver is enabled when CS

is logic [0]. CS should transition from a logic [1] to a logic [0]

state only when SCLK is a logic [0]. CS has an active internal

pullup, IUP.

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