Analog Integrated Circuit Device Data

Freescale Semiconductor

21

33874

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

OPEN LOAD FAULT (NON-LATCHING)

The 33874 incorporates open load detection circuitry on

the output. Output open load fault (OLF) is detected and

reported as a fault condition when the output is disabled

(OFF). The open load fault is detected and latched into the

status register after the internal gate voltage is pulled low

enough to turn OFF the output. The OLF fault bit is set in the

status register. If the open load fault is removed, the status

register will be cleared after reading the register.

The open load protection can be disabled through SPI

(bit OL_DIS).

It is recommended to disable open load

circuitry in case of a permanent disconnected load.

REVERSE BATTERY

The output survives the application of reverse voltage as

low as -16V. Under these conditions, the output’s gate is

enhanced to keep the junction temperature less than 150°C.

The ON resistance of the output is fairly similar to that in the

Normal mode. No additional passive components are

required except on VDD.

GROUND DISCONNECT PROTECTION

In the event the 33874 ground is disconnected from load

ground, the device protects itself and safely turns OFF the

output regardless of the state of the output at the time of

disconnection. A 10K

Ω resistor needs to be added between

the wake pin and the rest of the circuitry in order to ensure

that the device turns off in case of ground disconnect and to

prevent this pin to exceed its maximum ratings.

Current limit resistors in the digital input lines protect the

digital supply against excessive current (10k

Ω typical).

Table 7. Device behavior in case of Under-voltage

Quad High Side

Switch

(VPWR Battery

Voltage)

∗∗

State

UV Enable

IN[0:3] = 0

(Falling VPWR)

UV Enable

IN[0:3] = 0

(Rising VPWR)

UV Enable

IN_x*** = 1

(Falling VPWR)

UV Enable

IN_x*** = 1

(Rising VPWR)

UV Disable

IN[0:3] = 0

(Falling or

Rising VPWR)

UV Disable

IN_x*** = 1

(Falling or

Rising VPWR)

VPWR > VPWRUV

Output State

OFF

OFF

ON

OFF

OFF

ON

FS State

1

1

1

0

1

1

SPI Fault Register

UVF Bit

0

1 until next read

0

1

0 (falling)

1 until next

read (rising)

0 (falling)

1 until next

read (rising)

VPWRUV > VPWR

> UVPOR

Output State

OFF

OFF

OFF

OFF

OFF

ON

FS State

0

0

0

0

1

1

SPI Fault Register

UVF Bit

1

1

1

1

1

1

UVPOR > VPWR >

2.5V

∗

Output State

OFF

OFF

OFF

OFF

OFF

ON

FS State

1

1

1

1

1

1

SPI Fault Register

UVF Bit

1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read

2.5V > VPWR > 0V

Output State

OFF

OFF

OFF

OFF

OFF

OFF

FS State

1

1

1

1

1

1

SPI Fault Register

UVF Bit

1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read

Comments

UV fault is

not latched

UV fault is

not latched

UV fault

is latched

∗ = Typical value; not guaranteed

*** = IN_x is equivalent to IN_x direct input or IN_spi_s SPI input.