SC173AEVB datasheet(12/26 Pages) SEMTECH

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Hi-Side

and

Lo-Side

Gate

Drivers

PWM

On-Shot Timing

Generator

Time = K x VOUT/VIN

VOUT

VIN

REF

COUT

VIN

ESR

VOUT

VLX

LPF

RTON

The SC173A uses an external resistor to set the on-time

which indirectly sets the frequency. The on-time can

be programmed to provide operating frequency from

200kHz to 1MHz using a resistor between the TON pin

and ground. The resistor value is

selected by the fol-

lowing equation.

OUT Voltage Selection

The switcher output voltage is regulated by comparing

OUT as seen through a resistor divider at the FB pin to

the internal 750mV reference voltage, see Figure 3.

Figure 3 — Output Voltage Selection

Note that this control method regulates the valley of the

output ripple voltage, not the DC value. The DC output

voltage V

OUT is offset by the output ripple according to

the following equation.

Figure 2 — On-Time Generation

TON

25pF

⋅

VOUT

To FB pin

0.75V

RIPPLE

OUT













⋅

Enable Input

The EN input is used to enable or disable the switching

regulator. When EN is low (grounded), the switching reg-

ulator is off and in its lowest power state. When off, the

output power switches are tri-stated.

When EN is pulled high (above 1V), or permitted to float,

the switching regulator turns on with automatic power

save enabled.

Smart Power Save Protection

Active loads may leak current from a higher voltage

into the switcher output. Under light load conditions

with power save enabled, this can force V

OUT to slowly

rise and reach the over-voltage threshold, resulting in a

hard shutdown. Smart power save prevents this condi-

tion. When the FB voltage exceeds 10% above nominal

(exceeds 825mV), the device immediately disables powe

save, and DL drives high to turn on the low-side MOSFET.

This draws current from V

OUT through the inductor and

causes V

OUT to fall. When VFB drops back to the 750mV trip

point, a normal T

ON switching cycle begins. This method

prevents a hard OVP shutdown and also cycles energy

from V

OUT back to VIN. Figure 4 shows typical waveforms

for the Smart Power Save feature.

Figure 4 — Smart Power Save

Current Limit Protection

The device features fixed current limiting, which is ac-

complished by using the R

DS(ON) of the lower MOSFET for

current sensing. While the low-side MOSFET is on, the

Applications Information (continued)

threshold

High-side

Drive (DH)

Low-side

Drive (DL)

VOUT drifts up to due to leakage

current flowing into COUT

DH and DL off

DL turns on when Smart

PSAVE threshold is reached

Smart Power Save

Threshold (825mV)

DL turns off when FB

threshold is reached

Single DH on-time pulse

after DL turn-off

VOUT discharges via inductor

and low-side MOSFET

Normal DL pulse after DH

on-time pulse

Normal VOUT ripple

SC173A

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