LC651202F datasheet(21/35 Pages) SANYO

21 / 35 page

No. 5190-21/35

LC651204N/F/L, LC651202N/F/L

Parameter

Symbol

Conditions

Applicable pins/notes

Ratings

min

typ

max

Unit

Oscillator characteristics

Ceramic oscillator

Oscillator frequency

fCFOSC

Figure 2, fo = 4 MHz *5

OSC1, OSC2

3840

4000

4160

kHz

Oscillator stabilization

tCFS

Figure 3, fo = 4 MHz

time

Pull-up resistors

Output n-channel transistor off

I/O ports

RPP

Vin = VSS, VDD = 5 V

Ports with pull-up

Ω

resistor specifications

RES

Vin = VSS, VDD = 5 V

RES

100

250

400

Ω

External reset

characteristics

Reset time

tRST

See

Figure 4.

f = 1 MHz

Pin capacitance

With all pins other than the pin being measured at

VIN = VSS

Serial clock

Input clock cycle time

tCKCY (1)

Figure 5

SCK

2.0

µs

Output clock cycle time

tCKCY (2)

Figure 5

SCK

× T

CYC

µs

Input clock low-level

tCKL (1)

Figure 5

SCK

0.6

µs

pulse width

Output clock low-level

tCKL (2)

Figure 5

SCK

× T

CYC

µs

pulse width

Input clock high-level

tCKH (1)

Figure 5

SCK

0.6

µs

pulse width

Output clock high-level

tCKH (2)

Figure 5

SCK

× T

CYC

µs

pulse width

Serial input

Data setup time

tICK

Stipulated with respect to the rising edge of SCK.

0.2

µs

Data hold time

tCKI

Figure 5

0.2

µs

Serial output

Stipulated with respect to the falling edge of SCK.

Output delay time

tCKO

For n-channel open-drain outputs only. External

0.4

µs

resistance: 1 k

Ω, external capacitance: 50 pF. Figure 5

Pulse output

Period

tPCY

Figure 6

PE0

× T

CYC

µs

Tcyc = 4

× the system clock period

PE0

× T

CYC

µs

High-level pulse width

tPH

For n-channel open-drain outputs only:

±10%

External resistance: 1 k

Ω, external capacitance: 50 pF

Low-level pulse width

tPL

PE0

× T

CYC

µs

±10%

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