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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADC1413D датащи(PDF) 35 Page - NXP Semiconductors |
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ADC1413D датащи(HTML) 35 Page - NXP Semiconductors |
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35 / 43 page  ADC1413D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 February 2011 35 of 43 NXP Semiconductors ADC1413D series Dual 14-bit ADC; serial JESD204A interface Table 47. Cfg_02_2_LID (address 082Dh) Default values are highlighted. Bit Symbol Access Value Description 7 to 5 - - 000 not used 4 to 0 LID[4:0] R/W 11100 defines lane 1 identification number Table 48. Cfg01_13_FCHK (address 084Ch) Default values are highlighted. Bit Symbol Access Value Description 7 to 0 FCHK[7:0] R 00000000 defines the checksum value for lane 0 checksum corresponds to the sum of all the link configuration parameters modulo 256 (as defined in JEDEC Standard No.204A) Table 49. Cfg02_13_FCHK (address 084Dh) Default values are highlighted. Bit Symbol Access Value Description 7 to 0 FCHK[7:0] R 00000000 defines the checksum value for lane 1 checksum corresponds to the sum of all the link configuration parameters module 256 (as defined in JEDEC Standard No.204A) Table 50. Lane0_0_Ctrl (address 0870h) Default values are highlighted. Bit Symbol Access Value Description 7 - - 0 not used 6 SCR_IN_MODE R/W defines the input type for scrambler and 8-bit/10-bit units: 0 (reset) (normal mode) = input of the scrambler and 8-bit/10-bit units is the output of the frame assembly unit. 1 input of the scrambler and 8-bit/10-bit units is the PRBS generator (PRBS type is defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register) 5 to 4 LANE_MODE[1:0] R/W defines output type of lane output unit: 00 (reset) normal mode: lane output is the 8-bit/10-bit output unit 01 constant mode: lane output is set to a constant (0 0) 10 toggle mode: lane output is toggling between 0 0 and 0 1 11 PRBS mode: lane output is the PRBS generator (PRBS type is defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register) 3 - - 0 not used 2 LANE_POL R/W defines lane polarity: 0 lane polarity is normal 1 lane polarity is inverted 1 LANE_CLK_POS_EDGE R/W defines lane clock polarity: 0 lane clock provided to the serializer is active on positive edge 1 lane clock provided to the serializer is active on negative edge |
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