ADC1413D datasheet(21/43 Pages) NXP

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ADC1413D_SER

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Product data sheet

Rev. 5 — 9 February 2011

21 of 43

NXP Semiconductors

ADC1413D series

Dual 14-bit ADC; serial JESD204A interface

Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If

single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit

SE_SEL.

If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin

should be connected to ground via a capacitor.

11.3.3 Duty cycle stabilizer

The duty cycle stabilizer can improve the overall performance of the ADC by

compensating the input clock signal duty cycle. When the duty cycle stabilizer is active

(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of

between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled

(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and

55 %.

11.3.4 Clock input divider

The ADC1413D contains an input clock divider that divides the incoming clock by a factor

of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to

deliver a higher clock frequency with better jitter performance, leading to a better SNR

result once acquisition has been performed.

11.4 Digital outputs

11.4.1 Serial output equivalent circuit

The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,

both must be fed from the same supply.

The output should be terminated when 100

 (typical) is reached at the receiver side.

Table 12.

Duty cycle stabilizer

Bit DCS_EN

Description

duty cycle stabilizer disable

duty cycle stabilizer enable

Fig 19. CML output connection to the receiver (DC-coupled)

VDDD

CMLPA/CLMPB

CMLNA/CLMNB

AGND

005aaa082

12 mA to 26 mA

100

RECEIVER

−

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