XMEGAD datasheet(13/309 Pages) ATMEL

13 / 309 page

8210B–AVR–04/10

XMEGA D

3.12.2

Sequence for execution of protected SPM/LPM

The application code writes the signature for execution of protected SPM/LPM to the

CCP register.

Within 4 instruction cycles, the application code must execute the appropriate instruc-

tion. The protected change is immediately disabled if the CPU performs write

operations to the data memory, or if SLEEP is executed.

Once the correct signature is written by the CPU, interrupts will be ignored for the configuration

change enable period. Any interrupt request (including Non-Maskable Interrupts) during the

CPP period will set the corresponding interrupt flag as normal and the request is kept pending.

After the CPP period any pending interrupts are executed according to their level and priority.

3.13

Fuse Lock

For some system critical features it is possible to program a fuse to disable all changes in the

associated I/O control registers. If this is done, it will not be possible to change the registers from

the user software, and the fuse can only be reprogrammed using an external programmer.

Details on this are described in the datasheet module where this feature is available.

3.14

3.14.1

CCP - Configuration Change Protection Register

• Bit 7:0 - CCP[7:0] - Configuration Change Protection

The CCP register must be written with the correct signature to enable change of the protected

I/O register or execution of the protected instruction for a maximum of 4 CPU instruction cycles.

All interrupts are ignored during these cycles. After these cycles interrupts automatically handled

again by the CPU, and any pending interrupts will be executed according to their level and prior-

ity. When the Protected I/O register signature is written, CCP[0] will read as one as long as the

protected feature is enabled. Similarly when the Protected SPM/LPM signature is written CCP[1]

will read as one as long as the protected feature is enabled. CCP[7:2] will always be read as

zero. Table 3-1 on page 13 shows the signature for the various modes.

Bit

765

43210

+0x04

CCP[7:0]

CCP

Read/Write

WWWWWWWW

Initial Value

000

00000

Table 3-1.

Modes of CPU Change Protection

Signature

Group Configuration

Description

0x9D

SPM

Protected SPM/LPM

0xD8

IOREG

Protected IO register

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