ADL5502ACBZ-P2 datasheet(18/28 Pages) AD

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ADL5502

Rev. A | Page 18 of 28

Although some devices follow the ideal linear response at very

low input powers, not all devices continue the ideal linear

regression to a near 0 V y-intercept. Some devices exhibit

output responses that rapidly decrease and some flatten out.

With no RF signal applied, the ADL5502 has a typical output

offset of 15 mV (with a maximum of 100 mV) on VRMS and an

offset of 14 mV (with a maximum of 100 mV) on PEAK.

OUTPUT DRIVE CAPABILITY AND BUFFERING

The ADL5502 is capable of sourcing a VRMS output current of

approximately 3 mA. The output current is sourced through the

on-chip, 100 Ω series resistor; therefore, any load resistor forms

a voltage divider with this on-chip resistance. It is

recommended that the ADL5502 VRMS output drive high

resistive loads to preserve output swing. If an application requires

driving a low resistance load (as well as, in cases where increasing

the nominal conversion gain is desired), a buffering circuit is

necessary.

The PEAK output is designed to drive 2 pF loads. It is

recommended that the ADL5502 PEAK output drive low

capacitive loads to achieve a full output response time. The

effects of larger capacitive loads are particularly visible when

tracking envelopes during the falling transitions. When the

envelope is in a fall transition, the load capacitor discharges

through the on-chip load resistance of 1.9 kΩ. If the larger

capacitive load is unavoidable, the additional capacitance

can be counteracted by putting a shunt resistor to ground on

the PEAK output to allow for fast discharge. Such a shunt

resistor also makes the ADL5502 run higher current, and it

should not be reduced beyond 500 Ω.

When viewing the PEAK output on an oscilloscope, a low

capacitive FET probe should be used to interface with the

PEAK output. This reduces the capacitance presented to the

PEAK output and avoids the corresponding effects of larger

capacitive loads.

SELECTING THE SQUARE-DOMAIN FILTER AND

OUTPUT LOW-PASS FILTER

The internal filter capacitor of the ADL5502 provides averaging

in the square domain but leaves some residual ac on the output.

Signals with high peak-to-average ratios, such as W-CDMA or

CDMA2000, can produce ac residual levels on the ADL5502

VRMS dc output. To reduce the effects of these low frequency

components in the waveforms, some additional filtering is

required.

The square-domain filter capacitance of the ADL5502 can be

augmented by connecting a capacitor between Pin 1 (FLTR) and

Pin 2 (VPOS). In addition, the VRMS output of the ADL5502 can

be filtered directly by placing a capacitor between VRMS (Pin 7)

and ground. The PEAK output can be filtered by placing a

capacitor between Pin 6 (PEAK) and ground. The combination

of the on-chip, 100 Ω output series resistance and the external

shunt capacitor forms a low-pass filter to reduce the residual ac.

Figure 50 and Figure 51 show the effects on the residual ripple

vs. the output and square-domain filter capacitor values at two

communication standards with high peak-to-average ratios.

Note that there is a tradeoff between ac residual and response

time. Large filter capacitances increase the turn-on and pulse

response times (see Figure 36, Figure 38, Figure 39, Figure 41,

Figure 42, and Figure 43). Figure 52 shows the effect of the two

filtering options, the output filter and the square-domain filter

capacitor, on the pulse response time of the ADL5502. For more

information on the effects of the filter capacitances on the

response, see the Power Consumption, Enable, and Power-

On/Power-Off Response Time section.

100

1000

CAPACITANCE (nF)

CFLTR

COUT

Figure 50. AC Residual vs. CFLTR and COUT,

W-CDMA Forward Link (4.6 dB CF) Waveform

100

150

200

250

300

350

400

100

1000

CFLTR

COUT

CAPACITANCE (nF)

Figure 51. AC Residual vs. CFLTR and COUT,

W-CDMA Reverse Link (11.7 dB CF) Waveform

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