4-Level FSK Modem Data Pump

FX929A

© 1996 Consumer Microcircuits Limited

25

D/929A/4

Setting the PSAVE bit to '0' restores power to all of the chip circuitry. Note that the internal filters - and hence

the TxOp pin in transmit mode - will take about 20 symbol-times to settle after the PSAVE bit is taken from '1' to

'0'.

Mode Register B2: SSIEN - 'S' Symbol IRQ Enable

In receive mode, setting this bit to '1' causes the IRQ bit of the status register to be set to '1' whenever a new 'S'

symbol has been received. (The SRDY bit of the Status Register will also be set to '1' at the same time, and the

SVAL bits updated to reflect the received 'S' symbol.)

In transmit mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a 'S'

symbol has been transmitted. (The SRDY bit of the Status Register will also be set to '1' at the same time.)

Mode Register B1, 0: SSYM - 'S' Symbol To Be Transmitted

In transmit mode these two bits define the next 'S' symbol to be transmitted. These bits have no effect in

receive mode.

1.5.5.5 Status Register

This register may be read by the µC to determine the current state of the modem.

Status Register B7: IRQ - Interrupt Request

This bit is set to '1' by:

The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a

change to the Mode Register TXRXN or PSAVE bits.

or

The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a RESET task or by

changing the Mode Register TXRXN or PSAVE bits.

or

The Status Register DIBOVF bit going from '0' to '1'.

or

The Status Register SRDY bit being set to '1' (due to a 'S' symbol being received or transmitted) if

the Mode Register SSIEN bit is '1'.

The IRQ bit is cleared to '0' immediately after a read of the Status Register.

If the IRQNEN bit of the Mode Register is '1', then the chip IRQN output will be pulled low (to VSS) whenever

the IRQ bit is set to '1', and will go high impedance when the Status Register is read.

Status Register B6: BFREE - Data Block Buffer Free

This bit reflects the availability of the Data Block Buffer and is cleared to '0' whenever a task other than NULL or

RESET is written to the Command Register.

In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem

when the modem is ready for the µC to write new data to the Data Block Buffer and the next task to the

Command Register.