FX929AD2 datasheet(22/44 Pages) CMLMICRO

22 / 44 page

4-Level FSK Modem Data Pump

FX929A

D/929A/4

1.5.5.3

Control Register

This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock

extraction and signal level measurement circuits and the Frame Sync pattern recognition tolerance.

Control Register B7, B6: CKDIV - Clock Division Ratio

These bits control a frequency divider driven from the clock signal present at the XTALN pin, and hence

determine the nominal symbol rate. The table below shows how symbol rates of 2400/4800/9600 symbols/sec

may be obtained from common Xtal frequencies:

Xtal Frequency (MHz)

2.4576

4.9152

9.8304

Division Ratio:

Xtal Frequency/Symbol Rate

Symbol Rate (symbols/sec)

512

4800

9600

1024

2400

4800

9600

2048

2400

4800

4096

2400

Note: Device operation is not guaranteed below 2400 or above 9600 symbols/sec.

Control Register B5, B4: FSTOL - Frame Sync Tolerance

These two bits have no effect in transmit mode. In receive mode, they define the maximum number of

mismatches which will be allowed during a search for the Frame Sync pattern:

Mismatches allowed

Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol

'+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received symbol

value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for normal use.

Control Register B3, B2: LEVRES - Level Measurement Modes

These two bits have no effect in transmit mode. In receive mode they set the 'normal' operating mode of the

received signal amplitude and dc offset measuring circuits (the automatic sequencing of an AQLEV command

may temporarily override the 'normal' setting).

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