ISDN TA POTS Interface

CMX625

 2001 Consumer Microcircuits Limited

19

D/625/2

1.5.13 DTMF Tone Decoder

This block is enabled or disabled by bit 5 of the SETUP Register. If disabled, bit 4 and 5 of the STATUS

Register and bit 0 to bit 3 of the DTMF RX DATA Register are set to ‘0’ and no interrupts are generated.

When bit 5 of the SETUP Register is enabled and bit 4 of the INTERRUPT MASK Register is set to ‘1’ (i.e.

unmasked) a ‘detected tone’ generates an interrupt and bit 4 of the STATUS Register is set to ‘1’.

Reading the STATUS Register clears the IRQN output.

When bit 5 of the SETUP Register is enabled and bit 5 of the INTERRUPT MASK Register is unmasked

(logic ‘1’), a ‘status change’ of the decoder will generate an interrupt and bit 5 of the STATUS Register will

be set to ‘1’. The validity of the data is indicated by bit 4 of the STATUS Register. The decode truth table

is shown below. Reading the STATUS Register clears the IRQN output. An interrupt is not generated

when ‘no tone’ is detected.

DTMF RX DATA Register Bits 0 - 3

DTMF Tone Pairs

Bit 3

(D3)

Bit 2

(D2)

Bit 1

(D1)

Bit 0

(D0)

Lower Frequency

(Hz)

Upper Frequency

(Hz)

Keypad

Legend

0

0

0

0

941

1633

D

0

0

0

1

697

1209

1

0

0

1

0

697

1336

2

0

0

1

1

697

1477

3

0

1

0

0

770

1209

4

0

1

0

1

770

1336

5

0

1

1

0

770

1477

6

0

1

1

1

852

1209

7

1

0

0

0

852

1336

8

1

0

0

1

852

1477

9

1

0

1

0

941

1336

0

1

0

1

1

941

1209

*

1

1

0

0

941

1477

#

1

1

0

1

697

1633

A

1

1

1

0

770

1633

B

1

1

1

1

852

1633

C

A status change of the decoder and the generation of an interrupt (when the INTERRUPT MASK Register

bit 5 is unmasked) will occur both when a tone is first decoded and also when a tone, which was previously

present, is no longer decoded. In the latter case, bit 4 of the STATUS Register will be set to ‘0’ to indicate

that no tone was detected.

The decoded tone pair is indicated by bits 0-3 in the DTMF RX DATA Register.