WITH RATIOMETRIC OUTPUT

Rev B1, Page 6/22

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise stated

Item

Symbol

Parameter

Conditions

Unit

No.

Min.

Typ.

Max.

General

001

VDD

Supply Voltage

4.5

5

5.5

V

002

I(VDD)

Supply Current in VDD

PSMI = lo, other pins open

8

12

mA

003

I(VDD)sb

Standby Supply Current

PSMI = hi

200

µA

004

VDDon

Power-On Threshold

Increasing voltage VDD

3.0

4.1

V

005

VDDoff

Power-Down Threshold

Decreasing voltage VDD

2.6

3.9

V

006

VDDhys

Hysteresis

VDDhys = VDDon - VDDoff

200

mV

007

ton()1

Turn-On Delay Following

Power-On

Time to data valid after enabling,

1

ms

VDD: VDDoff → VDDon

008

ton()2

Turn-On Delay Following Standby Time to data valid after standby,

900

µs

PSMI: hi → lo

009

Vc()hi

Clamp Voltage hi at

PSMI, MA, SLI, NERR

VDD = 0 V; I() = 1 mA

0.3

1.6

V

010

Vc()hi

Clamp Voltage hi at

PSMO, LAO, SLO

VDD = 0 V; I() = 4 mA

0.3

1.6

V

011

Vc()lo

Clamp Voltage lo at

PSMI, PSMO, LAO, MA, SLO,

SLI, NERR, VDD, VZAP

I() = -4 mA

-1.5

-0.3

V

Hall Sensor Array

101

Hext

Operating Magnetic Field

Strength

At surface of chip

20

50

100

kA/m

102

RPM

Permissible RPM Speed

12 000

rpm

103

ferr()

Excessive Frequency Alarm

ENERR(1) = 1; NERR: hi → lo

1

kHz

104

fmag()

Magnetic Field Frequency

200

Hz

105

dsens

Diameter of Hall Sensor Array

2

mm

106

xpac

Chip Placement Tolerance

Versus DFN10 package outlines

-0.2

0.2

mm

107

φ

pac

Chip Tilt Angle

Versus DFN10 package outlines

-3

3

DEG

108

hpac

Distance Surface of Package to

Surface of Chip

DFN10 package

400

µm

Sine-To-Digital Converter

301

RES

Converter Resolution

Per 360 degree

8

bit

302

HYS

Converter Hysteresis

1.4

DEG

303

AAabs

Absolute Angle Accuracy

Magnet with 4 mm in diameter, axis centered to

chip

-3

3

DEG

D/A Converter And Ratiometric Output LAO

401

RES()

D/A Converter Resolution

MODE(1:0) = 00 (range 360°)

8

bit

MODE(1:0) = 01 (range 270°)

7.5

bit

MODE(1:0) = 10 (range 180°)

7

bit

MODE(1:0) = 11 (range 90°)

6

bit

402

Iload()

Permissible Output Current

-1

1

mA

403

dV0()hi

Output Voltage hi, Rail-To-Rail

dV0()hi = V(VDD) - V(LAO), MODE(3) = 0;

I() = -1 mA

170

mV

I() = 0 mA

85

mV

404

dV0()lo

Output Voltage lo, Rail-To-Rail

MODE(3) = 0;

I() = 1 mA

170

mV

I() = 0 mA

85

mV

405

dV1()hi

Output Voltage hi, 10/90% Range MODE(3) = 1; I() = -1...+1 mA

85

95

%VDD

406

dV1()lo

Output Voltage lo, 10/90% Range MODE(3) = 1; I() = -1...+1 mA

5

15

%VDD

407

Ilk()

Leakage Current

V(LAO) = 0...VDD, PSMI = hi

-5

5

µA

408

SR()hi

Slew Rate hi

V(LAO): 20% → 80% of range

2

V/µs

409

SR()lo

Slew Rate lo

V(LAO): 80% → 20% of range

2

V/µs

Zapping Input VZAP

501

Vt1()hi

Voltage Threshold hi vs. GND

2

V

502

Vt1()lo

Voltage Threshold lo vs. GND

0.8

V