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TLE4470GS датащи(PDF) 14 Page - Infineon Technologies AG |
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TLE4470GS датащи(HTML) 14 Page - Infineon Technologies AG |
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14 / 24 page ![]() Data Sheet 14 Rev. 1.2, 2008-03-20 TLE 4470 Input, Output The input capacitor C I is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with C I, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuits of the stand-by and main regulator, output capacitors C Q1 and CQ2 are necessary. Stability is guaranteed at values CQ1 ≥ 6 µF and C Q2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range. For the TLE 4470 G (PG-DSO-20) the output voltage V Q2 of the main regulator can be adjusted to 5 V ≤ V Q2,nom ≤ 20 V by connecting an external voltage divider to the voltage adjust pin ADJ2. For V Q2 = 5 V the voltage adjust pin has to be connected directly to the main output. For calculating V Q2 or R1 and R2 respectively the following equations can be used: V Q2 = VQ1 × (1 + R1 / R2)(1) or R 1 = R2 × (VQ2 / VQ1 - 1) (2) Disable The main regulator of the TLE 4470 can be switched OFF by a voltage above 2.3 V at pin DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor C D which can be calculated as follows: C D = (∆t × ID,c) / ∆V(3) Definitions: • C D = delay capacitor • ∆t = reset delay time • I D,c = charge current, typical 5 µA • ∆V = V DU, typical 1.8 V • V DU = upper delay switching threshold at CD for reset delay time The reset reaction time t rr is the time it takes the voltage regulator to set the reset out LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs for delay capacitor of 100 nF. For other values for C D the reaction time can be estimated using the following equation: t rr ≈ 20 s/F × CD (4) |
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