IR3522

Page 13

V3.01

IR3522 THEORY OF OPERATION

Block Diagram

The Block diagram of the IR3522 is shown in Figure 7. The following discussions are applicable to either output

plane unless otherwise specified.

SRD_PRESET#

Open Control

Loop

VCCL

IIN2

OCSET2

OC LIMIT COMPARAT OR2

IROSC

IROSC

OC LIMIT COMPARAT OR 1

IIN1

OCSET1

VCCL UVLO

SVI_OFF

IROSC

OPEN DAISY

PHSIN

PHSOUT

CLKOUT

PHSIN

IROSC

VREF1

ROSC

VID0

PHSOUT

CLKOUT

FAULT

IROSC

VREF1

ISOURCE

VREF BUFFER

AMPLIFIER

0.6V

ROSC BUFFER

AMPLIFIER

CURRENT

SOURCE

GE NERATOR

UV2

ISINK

OV1_2

VOUT1

25k

TRACK_FLT

OV2

+

-

+

-

25k

25k

25k

VOSEN2-

VOSEN2+

VOUT2

VCCL

T RACK FAULT

COMPARAT OR

275mV

315mV

VOUT 2 UV

COMPARAT OR

OVER VOLT AGE

COMPARAT OR 2

REMOT E SENSE

AMPLIFIER 2

Fault Latch

Control Logic

1.0 6V

SRD PRESET

SS_DI SCHARGED

DETECT PULSE1

2X IROSC

SS_DISCHARGED

ENABLE

VREF_TRACK

VCCL UVLO

3.9V

45uA

SS/DEL1

OC1

IDCHG

55uA

ICHG

TRACK_FLT

OV1-2

VCCL

PGBIAS

PGOOD

CROWBAR

25k

I NTERNAL_CROWBAR

SS/DEL

VREF1

EAOUT1

SOFT ST ART

CLAMP

ERROR

AMPLIFIER 1

FB1

DIS

1.4V

SRD_PRESET#

25k

25k

25k

25k

VOSEN1+

VOUT1

REMOT E SENSE

AMPLIFIER 1

VOSEN1-

UV1

OV1

+

-

260mV

OVER VOLT AGE

COMPARAT OR 1

VOUT 1 UV

COMPARAT OR

275mV

315mV

SS Comparators

I NTERNAL_CROWBAR

OPEN CONTROL 1

UV2

UV1

DLY _OUT

OPEN SENSE

LINE DETECT

CIRCUIT 1

OPEN CONTROL 2

OPEN DAISY

OPEN SENSE

OPEN CONTROL 1

OC DELAY

COUTER

VID1

VID0

VREF1

0

0

1.05V

0

1

1.2V

1

0

1.35V

1

1

1.5V

POWER-UP VREF1

CONT ROL

3.3V

VID3

VID3

D

CLK

Q

R

VAL ID I2C

COMMAND

OVE RRIDE

ARRIVE D

VID7

VREF1 CODE

ST ORAGE LAT CH

VID7

VOUT1

ENABLE

SVI ADDRESS

SDA

SCL

VID3

VID3

.

VID7

VID3

VID7

VID7

VREF_TRACK

SVI (Serial VID Int erface)

VREF1_FAST

VID2 OFF

VID1 OFF

D/A CONVERT ER

TRACK

CONTROL

VREF

CONTROL

VID7

1.65V

950mV

650mV

ADDR2

ADDR1

VID7

VID7

VID1

VID0

OPEN SENSE

OPEN

SENSE LINE

DETECT

CIRCUIT 2

SOFT STOP

SS_DISCHARGED

PHSOUT

OC2

VID7

VID7

DETECT PULSE1

1V

+

-

DIS

LGND

VCCL

ENABLE

ENABLE COMPARAT OR

3.99V

250nS

BL ANKING

1.65V

INT ERNAL

CIRCUIT BIAS

4.43V

VCCL UVL

COMPARAT OR

VCCL

DLY _OUT

OPEN CONTROL 2

SVI _OFF

INTERNAL_CROWBAR

FB2

EAOUT2

ERROR

AMPLIFIER 2

DIS

70mV

OC TIMEOUT

Figure 7 Block Diagram