IR3522

Page 21

V3.01

Over-Current Protection

fault is flagged after a delay programmed by Rocs (see Electrical Specification). The delay is required since over-

current conditions can occur as part of normal operation due to load transients or VID transitions.

voltage, the OCDELAY counter starts counting the PHSOUT pulses. If the over-current condition persists long

enough for the counter to reach the program number, the fault latch will be set which will then pull the error

amplifier’s output low to stop phase IC switching and will also de-assert the PGOOD signal. The SS/DEL capacitor

will then discharge by a 55 uA current. The output current is not controlled during the delay time. This latch can only

reset by either recycling the ENABLE pin or VID_OFF command.

VCCL Under Voltage Lockout (UVLO)

The IR3522 monitors the VCCL supply voltage to determine if the amplitude is proper to adequately drive the top

and bottom gates. As VCCL begins to rise during power up, the IC is allowed to power up when VCCL reaches 4.43

V (Typical). The ENABLE CLEARED fault latches will be released. If VCCL voltage drops below 3.99V (Typical) of

the set value, the ENABLE CLEARED fault latch will be set.

VID OFF Codes

SVID OFF codes will turn off the converter keeping the error amplifiers active and discharging SS/DEL through the

50uA discharge current allowing the outputs to discharge in a control manner (soft-stop). Upon receipt of a non-off

SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in Figure 10.

Power Good (PGOOD)

The PGOOD pin is an open-drain output and should have an external pull-up resistor. During soft start, PGOOD

remains low until the output voltage is in regulation and SS/DEL is above 3.9V. The PGOOD pin becomes low if any

fault is registered (see TABLE 5 for details). A high level at the PGOOD pin indicates that the converter is in

operation with no fault and ensures the output voltage is within regulation.

PGOOD monitors the output voltage. If any of the voltage planes fall out of regulation, PGOOD will become low, but

the VR continues to regulate its output voltages. Output voltage out-of-spec is defined as 315mV to 275mV below

nominal voltage. VID on-the-fly transition which is a voltage plane transitioning between one voltage associated with

one VID code and a voltage associated with another VID code is not considered to be out of specification.

Open Voltage Loop Detection

The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If

any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault

latch is set. The fault latch can only be cleared by cycling the ENABLE or the VID_OFF command.

Enable Input

Pulling the ENABLE pin below 0.8V sets the Fault Latch. Forcing ENABLE to a voltage above 1.65V allows the

SS/DEL pin to begin a power-up cycle.

Over Voltage Protection (OVP)

Output over-voltage might occur due to a high side MOSFET short or if the output voltage sense path is

compromised. If the over-voltage protection comparators sense that either VOUT1 pin voltage exceeds VREF1 by

260mV or VOUT2 exceeds VREF1, the over voltage fault latch is set which pulls the error amplifier output low to

turn off the converter power stage. The IR3522 communicates an OVP condition to the system by raising the

CROWBAR pin voltage to within V(VCCL) – 0.2 V. With the error amplifiers outputs low, the low-side MOSFET