ST10F272Z2T3 datasheet(151/189 Pages) STMICROELECTRONICS

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ST10F272Z2

Electrical characteristics

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Data about maximum input leakage current at each pin are provided in the Data Sheet

(Electrical Characteristics section). Input leakage is greatest at high operating temperatures,

and in general it decreases by one half for each 10°C decrease in temperature.

Considering that, for a 10-bit A/D converter one count is about 5mV (assuming

VAREF = 5 V), an input leakage of 100nA acting though an RL = 50kΩ of external resistance

leads to an error of exactly one count (5mV); if the resistance were 100k

Ω the error would

become two counts.

Eventual additional leakage due to external clamping diodes must also be taken into

account in computing the total leakage affecting the A/D converter measurements. Another

contribution to the total leakage is represented by the charge sharing effects with the

sampling capacitance: being CS substantially a switched capacitance, with a frequency

equal to the conversion rate of a single channel (maximum when fixed channel continuous

conversion mode is selected), it can be seen as a resistive path to ground. For instance,

assuming a conversion rate of 250kHz, with CS equal to 4pF, a resistance of 1MΩ is

obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered

channel). To minimize the error induced by the voltage partitioning between this resistance

(sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit

must be designed to respect the following relation:

The formula above provides a constraints for external network design, in particular on

resistive path.

A second aspect involving the capacitance network shall be considered. Assuming the three

capacitances CF, CP1 and CP2 initially charged at the source voltage VA (refer to the

equivalent circuit reported in Figure 43), when the sampling phase is started (A/D switch

close), a charge sharing phenomena is installed.

Figure 44.

Charge sharing timing diagram during sampling phase

In particular two different transient periods can be distinguished (see Figure 44):

●

A first and quick charge transfer from the internal capacitance CP1 and CP2 to the

sampling capacitance CS occurs (CS is supposed initially completely discharged):

considering a worst case (since the time constant in reality would be faster) in which

CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitance CP and CS

are in series, and the time constant is:

------------------------------------------------------------------------------

⋅

---LSB

VA1

VA2

VCS

Voltage Transient on CS

∆V < 0.5 LSB

τ1 < (RSW + RAD) CS << TS

τ2 = RL (CS + CP1 + CP2)

τ1 RSW RAD

()

CP CS

⋅

CP CS

-----------------------

⋅

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