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Datasheet

Introduction

The Intel® Celeron® D processors 365, 360, 356, 352, and 347 are single-core desktop

processors on the 65 nm process. The processor uses Flip-Chip Land Grid Array (FC-

LGA6) package technology, and plugs into the LGA775 socket.

Note:

In this document the Intel® Celeron® D processor 300 sequence on the 65 nm process

is referred to as the “Celeron D processor” or simply “the processor.”

Note:

In this document, unless otherwise specified, the Intel® Celeron® D processor 300

sequence refers to Intel Celeron D processors 365, 360, 356, 352, and 347.

The Celeron D processor supports Intel® 64 architecture as an enhancement to Intel’s

IA-32 architecture. This enhancement enables the processor to execute operating

systems and applications written to take advantage of Intel 64 architecture. Further

details on the 64-bit extension architecture and programming model can be found in

the Intel® Extended Memory 64 Technology Software Developer Guide at http://

developer.intel.com/technology/64bitextensions/.

The Celeron D processor is based on the Intel 32-bit microarchitecture and maintains

the tradition of compatibility with IA-32 software. It has the Front Side Bus (FSB) data

transfer speed at 533 MB/s and Level 2 cache size of 512 KB.

The Celeron D processor also includes the Execute Disable Bit capability. This feature,

combined with a supported operating system, allows memory to be marked as

executable or non-executable. If code attempts to run in non-executable memory, the

processor raises an error to the operating system. This feature can prevent some

classes of viruses or worms that exploit buffer over run vulnerabilities and can, thus,

help improve the overall security of the system. See the Intel® Architecture Software

Developer's Manual for more detailed information.

Intel will enable support components for the Celeron D processor including heatsink,

heatsink retention mechanism, and socket. Manufacturability is a high priority; hence,

mechanical assembly may be completed from the top of the baseboard and should not

require any special tooling.

The processor includes an address bus power down capability that removes power from

the address and data signals when the FSB is not in use. This feature is always enabled

on the processor.

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in

the active state when driven to a low level. For example, when RESET# is low, a reset

has been requested. Conversely, when NMI is high, a nonmaskable interrupt has

occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as address or data), the ‘#’ symbol implies

that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and

D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front Side Bus” refers to the interface between the processor and system core logic

(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,

memory, and I/O.

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