82801BA datasheet(49/498 Pages) INTEL

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-13

Signal Description

2.19

Power and Ground

GPIO[5]

Not implemented.

GPIO[4:3]

Fixed as Input only. Main power well. Can be used instead as PIRQ[G:F]#.

GPIO[2]

Not implemented.

GPIO[1:0]

Fixed as Input only. Main Power Well. Can instead be used for PC/PCI

REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#.

Table 2-19. Power and Ground Signals

Name

Description

Vcc3_3

3.3V supply for Core well I/O buffers. This power may be shut off in S3, S5 or G3 states.

Vcc1_8

1.8V supply for Core well logic. This power may be shut off in S3, S5 or G3 states.

V5REF

Reference for 5V tolerance on Core well inputs. This power may be shut off in S3, S5 or

G3 states.

HUBREF

0.9V reference for the hub interface. This power may be shut off in S3, S5 or G3 states.

VccSus3_3

3.3V supply for Resume well I/O buffers. This power is not expected to be shut off unless

power is removed.

•

82801BA ICH2: The system is unplugged.

•

82801BAM ICH2-M: The main battery is removed or completely drained and AC

power is not available.

VccSus1_8

1.8V supply for Resume well logic. This power is not expected to be shut off unless power

is removed.

•

82801BA ICH2: The system is unplugged.

•

82801BAM ICH2-M: The main battery is removed or completely drained and AC

power is not available.

V5REF_SUS

Reference for 5V tolerance on Resume well inputs. This power is not expected to be shut

off unless power is removed.

•

82801BA ICH2: The system is unplugged. Note that V5REF_SUS only affects 5V

tolerance for the USB OC[3:0]# pins and can be connected to VccSUS3_3 if 5V

tolerance on these signals is not required.

•

82801BAM ICH2-M: The main battery is removed or completely drained and AC

power is not available.

VccRTC

3.3V (can drop to 2.0V min. in G3 state) supply for the RTC well. This power is not

expected to be shut off unless the RTC battery is removed or completely drained.

Note: Implementations should not attempt to clear CMOS by using a jumper to pull

VccRTC low. Clearing CMOS in an ICH2-based platform can be done by using a jumper

on RTCRST# or GPI, or using SAFEMODE strap.

VccLAN3_3

(ICH2-M only)

3.3V supply for LAN Connect interface buffers. This is a separate power plane that may or

may not be energized in S3–S5 states depending upon the presence or absence of AC

power and network connectivity. This plane must be on in S0 and S1.

VccLAN1_8

(ICH2-M only)

1.8V supply for LAN controller logic. This is a separate power plane that may or may not

be energized in S3–S5 states depending upon the presence or absence of AC power and

network connectivity. This plane must be on in S0 and S1.

VBIAS

RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is

mirrored throughout the oscillator and buffer circuitry. See Section 2.20.3.

V_CPU_IO

processor interface outputs.

Vss

Grounds.

Table 2-18. General Purpose I/O Signals (Continued)

Name

Type

Description

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