82801BA datasheet(21/498 Pages) INTEL

21 / 498 page

82801BA ICH2 and 82801BAM ICH2-M

Datasheet

xxi

Figures

2-1

Required External RTC Circuit....................................................................2-16

2-2

Example V5REF Sequencing Circuit ..........................................................2-16

4-1

ICH2 and System Clock Domains................................................................4-1

4-2

Conceptual System Clock Diagram (82801BA ICH2 and

82801BAM ICH2-M)......................................................................................4-2

5-1

Primary Device Status Register Error Reporting Logic.................................5-3

5-2

Secondary Status Register Error Reporting Logic ........................................5-3

5-3

NMI# Generation Logic .................................................................................5-4

5-4

Integrated LAN Controller Block Diagram.....................................................5-7

5-5

64-Word EEPROM Read Instruction Waveform .........................................5-17

5-6

LPC Interface Diagram ...............................................................................5-21

5-7

Typical Timing for LFRAME# ......................................................................5-24

5-8

Abort Mechanism ........................................................................................5-24

5-9

ICH2 DMA Controller ..................................................................................5-26

5-10

DMA Serial Channel Passing Protocol .......................................................5-30

5-11

DMA Request Assertion Through LDRQ# ..................................................5-34

5-12

Coprocessor Error Timing Diagram ............................................................5-67

5-13

Signal Strapping..........................................................................................5-70

5-14

Intel® SpeedStep™ Block Diagram (82801BAM ICH2-M only) ..................5-85

5-15

Physical Region Descriptor Table Entry ...................................................5-101

5-16

Transfer Descriptor ...................................................................................5-109

5-17

Example Queue Conditions ......................................................................5-116

5-18

USB Data Encoding ..................................................................................5-119

5-19

USB Legacy Keyboard Flow Diagram ......................................................5-128

5-20

ICH2 Based AC’97 2.1..............................................................................5-143

5-21

AC’97 2.1 Controller-Codec Connection...................................................5-144

5-22

AC-link Protocol ........................................................................................5-145

5-23

AC-link Powerdown Timing .......................................................................5-151

5-24

SDIN Wake Signaling ...............................................................................5-152

5-25

FWH Memory Cycle Preamble .................................................................5-155

5-26

Single Byte Read ......................................................................................5-155

5-27

Single Byte Write ......................................................................................5-156

15-1

ICH2 82801BA and ICH2-M 82801BAM Ballout

(Top view — Left side) ................................................................................15-2

15-2

ICH2 82801BA and ICH2-M 82801BAM Ballout

(Top view — Right side)..............................................................................15-3

15-3

ICH2 / ICH2-M Package (Top and Side Views) ........................................15-14

15-4

ICH2 / ICH2-M Package (Bottom View)....................................................15-15

16-1

Clock Timing .............................................................................................16-18

16-2

Valid Delay From Rising Clock Edge ........................................................16-18

16-3

Setup And Hold Times ..............................................................................16-18

16-4

Float Delay................................................................................................16-18

16-5

Pulse Width...............................................................................................16-19

16-6

Output Enable Delay.................................................................................16-19

16-7

IDE PIO Mode...........................................................................................16-19

16-8

IDE Multiword DMA...................................................................................16-20

16-9

Ultra ATA Mode (Drive Initiating a Burst Read) ........................................16-20

16-10

Ultra ATA Mode (Sustained Burst)............................................................16-21

16-11

Ultra ATA Mode (Pausing a DMA Burst)...................................................16-21

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