M24256-DR datasheet(6/42 Pages) STMICROELECTRONICS

номер детали	M24256-DR

подробное описание детали	256 Kbit serial I짼C bus EEPROM with three Chip Enable lines

PDF	42 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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Description

M24256-BF, M24256-BR, M24256-BW, M24256-DR

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Doc ID 6757 Rev 21

Description

The M24256-Bx devices are I2C-compatible electrically erasable programmable memories

(EEPROM). They are organized as 32 Kb × 8 bits.

The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance

with the I2C bus definition. The M24256-DR also decodes the type identifier code (1011)

when accessing the identification page.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a device select code and Read/Write

bit (RW) (as described in Table 2), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Figure 1.

Logic diagram

Table 1.

Signal names

Signal name

Function

Direction

E0, E1, E2

Chip Enable

Inputs

SDA

Serial Data

I/O

SCL

Serial Clock

Input

Write Control

Input

VCC

Supply voltage

VSS

Ground

M24256-DR датащи(PDF) 6 Page - STMicroelectronics