DS2149

8 of 32

PIN

NAME

I/O

FUNCTION

17

L3

I

LBO3. LBO0 through LBO3 are used to select transmitter output pulse, and receiver

gain.

18

NLOOP

O

Network Loopback Active. Output high when RLB is activated by in-band loop-up

command present for 5 seconds. Output is reset when RLP is deactivated by in-band

loop-down command present for 5 seconds. Activation of remote loopback through

hardware pin 26 or control bit RLB releases the NLOOP output.

19/

20

RTIP/

RRING

I

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect

through a 1:1 transformer to the line (Section 6).

21

VDD

—

Positive Supply. 5V ±5%. See also VSM pin 10.

22

VSS

—

Signal Ground

L0

LBO0. LBO0 through LBO3 are used to select transmitter output pulse, and receiver

gain.

23

INT

I/O

INT. Used to alert the host when one or more bits are set in the status register.

L1

LBO1. LBO0 through LBO3 are used to select transmitter output pulse, and receiver

gain.

24

SDI

I

Serial Data Input. Input for serial address and data stream. Sampled on rising of

SCLK.

L2

LBO2. LBO0 through LBO3 are used to select transmitter output pulse, and receiver

gain.

25

SDO

O

Serial Data Output. Updated on falling edge of SCLK if CLKE is connected high.

Updated on rising edge of SCLK if CLKE is connected low. SDO is high-Z during

write cycle or when CS is high.

RLB

Remote Loopback. Used to invoke remote loopback. When held high, the transmitter

inputs are ignored and inbound data received at RTIP and RRING is routed to the

transmitter outputs, TTIP and TRING and transmitted at the inbound recovered clock

rate.

NLB

Network Loopback. Enables network loopback detection when RLB floats.

26

CS

Chip Select. Must be low to read or write to the device.

CS is an active-low signal.

LLB

Local Loopback. Used to invoke local loopback. When held high, digital inputs

TPOS and TNEG are looped back to RPOS and RNEG, through the jitter attenuator

if enabled. Floating this input invokes analog loopback. The analog output signal at

TTIP and TRING is routed to the receive inputs RTIP and RRING.

27

SCLK

Serial Clock Input. Input clock to operate serial port. Max clock rate, 2.048MHz.

TAIS

Transmit AIS. Input high forces transmitter to output unframed all ones. Unavailable

in remote loopback.

QRSS

QRSS. Floating this pin enables QRSS pattern generator and detector. Input low

enables normal transmission of data.

28

CLKE

Clock Edge Select

0 = Update RNEG/RPOS on falling edge of RCLK, SDO updated on rising edge of

SCLK.

1 = Update RNEG/RPOS on rising edge of RCLK, SDO updated on falling edge of

SCLK.

Note 1: G.703 requires an accuracy of ±50ppm for T1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces.

Note 2: Input pins have three operating modes.