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DS2149

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Table 2-C. Signal Descriptions

NAME

I/O

FUNCTION

MCLK

Master Clock. A 1.544MHz clock source with TTL levels is applied at this pin. This

clock is used internally for both clock/data recovery and for jitter attenuation.1

TCLK

Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit

side formatter. Can be sourced internally by MCLK or RCLK.

TPOS

Transmit Positive Data. Sampled on the falling edge of TCLK for data to be

transmitted out onto the line.

TDATA

Transmit NRZ Data. Sampled on the falling edge of TCLK for data to be transmitted

onto the line.

INSLER

Transmit Insert Logic Error. Rising edge on INSLER inserts a logic error into the

outbound QRSS pattern. Sampled on falling edge of TCLK.

TNEG

Transmit Negative Data. Sampled on the falling edge of TCLK for data to be

transmitted out onto the line.

INSBPV

Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge of TCLK.

Rising edge inserts one BPV.

MODE1

Mode Select 1. Connect low to select hardware mode. Connect high to select serial

port mode. See also MODE0.

RNEG

Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge

(CCR2.0 = 1) of RCLK with the bipolar data out of the line interface. Always valid

on rising edge of RCLK in hardware mode.

BPV

Receive Bipolar Violation. Transitions high for one clock cycle marking an inbound

bipolar violation. Valid on rising edge of RCLK.

RPOS

Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge

(CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Always valid on

rising edge of RCLK in hardware mode.

RDATA

Receive Data. RDATA is the NRZ output from the line interface. Set NRZE

(CCR1.6) to a 1 for NRZ applications. In NRZ mode, data is output on RPOS while a

received error causes a positive-going pulse synchronous with RCLK at RNEG

(Section 6).

RCLK

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in

absence of signal at RTIP and RRING.

MODE0

Mode Select 0. Set high to disable all output pins (including the serial control port).

Set low for normal operation. Useful in board level testing. See also MODE1.

VSM

Voltage Supply Mode. Connect high for 5V operation. Has 10k

W pullup.

JASEL

Jitter Attenuator Select

0 = Place the jitter attenuator on the transmit side

1 = Place the jitter attenuator on the receive side

Float = Disable jitter attenuator

Not used in software mode

RCL

Receive Carrier Loss. An output that toggles high during a receive carrier loss.

QPD

QPD. Output high when QRSS detector is searching for QRSS data pattern. Output

high for one-half clock cycle on bit error. Connect to external counter to count bit

errors.

13/

TTIP/

TRING

Transmit Tip and Ring. Analog line driver outputs. These pins connect through a

step-up transformer to the line (Section 5).

VSS

—

Ground for Transmitter Block

TVDD

—

Positive Supply. 5.0V ±5% for the transmitter block. See also VSM pin 10.

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