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VSC060

Data Sheet

Revision 4.1

January 2008

3.2.87 6Dh: Fan Speed Count Overflow 15 (FSCO15)

The following table shows the bit assignments for the Fan Speed Count Overflow 15 register. This register

functions same the Fan Speed Count Overflow 0 register except it affects the P2.7 pin.

3.2.88 6Eh: Fan Speed Current Count 15 (FSCC15)

The following table shows the bit assignments for the Fan Speed Current Count 15 register. This register

functions the same as Fan Speed Current Count 0 except it affects the P2.7 pin.

FSCO15

Address:

6Dh

Reset Value:

0000_0000b

Bit

Bit Label

Access

Description

7:0

FSCO7-0

R/W

Fan Speed Count Overflow

These eight bits are compared to the 8-bit fan speed counter. If the counter

exceeds this value, an interrupt is generated.

This register should be loaded prior to setting the FSCEN bit in the FSC15

The overflow count value can be determined using the following equation,

where FF% is equal to the percentage of nominal RPM that constitutes a fan

failure:

Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%)

Based on the above equation, a divisor of 8, and a detected fan failure at 70%

of nominal RPM, the fan speed monitoring logic can support a low-end nominal

RPM of 850. High-end RPM values are basically unlimited; however, counter

resolution is diminished above 8000 RPM.

FSCC15

Address:

6Eh

Reset Value:

0000_0000b

Bit

Bit Label

Access

Description

7:0

FSCC7-0

These eight bits, when enabled by setting the FSCEN bit in the FSC15 register,

provide the user with an accurate binary fan speed count value that can be

used to determine the current RPM value of the fan. A minimum of one

complete revolution of the fan is required to generate an accurate fan speed

count value. The following equation can be used to determine the current RPM

value of the fan:

RPM = (1,200,000) / (Decimal count value × divisor)

When the result of a read of this register is 00h, an accurate fan speed count

value is not generated, indicating that the fan has not completed a minimum of

one revolution.

When the result of a read of this register is FFh, the fan is rotating very slowly

or no tachometer pulses are present.

When operating in a polled mode, with the FSIEN bit reset in the FSC15

once per revolution of the fan.

When operating in an Interrupt mode with the FSIEN bit set in the FSC15

count, once per revolution of the fan, until an interrupt is generated. After the

interrupt is generated, the value remains stable until the interrupt is cleared.

When the interrupt is cleared, this register is also cleared, indicating that a

valid RPM value is in the process of being generated.

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