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VSC060

Data Sheet

Revision 4.1

January 2008

3.2.74 5Ch: Fan Speed Control 11 (FSC11)

The following table shows the bit assignments for the Fan Speed Control 11 register. This register

functions same the Fan Speed Control 0 register except it affects the P2.3 pin.

FSC11

Address:

5Ch

Reset Value:

00XX_XX00b

Bit

Bit Label

Access

Description

FSCEN

R/W

Fan Speed Control Enable

When this bit is set, P2.3 is automatically configured to provide a fan speed

monitoring input. Configurations for this I/O pin that may have been previously

enabled through other control registers are overridden, except for the bypass

select function (bits 6 and 5 of the appropriate bit control registers). If the

appropriate bypass bits are set, the odd-numbered fan speed input pins (P1.1,

P1.3, P1.5, P1.7, P2.1, P2.3, P2.5, or P2.7) are configured as outputs.

When this bit is reset, the remaining bits in this register have no effect on the

operation of P2.3.

When enabled as a fan speed monitoring input, pulses from the fan tachometer

output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored

in bits 1 and 0 of this register allow the user to select one of four nominal RPM

values based on fan tachometer outputs, which pulse twice per revolution. The

FSCC11 register provides the user with an accurate binary fan speed count

value that can be used to determine the current RPM value of the fan.

Incoming pulses are filtered and conditioned to accommodate the slow rise and

fall times typical of fan tachometer outputs.

The maximum input signal is limited to a range of VSS to VDD. If this input is

supplied from a fan tachometer output that exceeds this range, external

components are required to limit the signal to an acceptable range.

FSIEN

R/W

Fan Speed Interrupt Enable

When this bit is set, the P2.3 input generates an interrupt if the 8-bit counter

value is greater than or equal to the count overflow value loaded into the

FSCO11 register. If this condition occurs, the INT# pin asserts and a binary

value equal to the address of this register appears in the BCIS register. When

this bit is reset, the fan speed monitoring logic does not generate an interrupt

condition.

5:2

RES

Reserved.

1:0

FD1-0

R/W

Fan Divisor

These two bits determine the divisor value used to determine the correct range

of RPM values supplied to the 8-bit fan speed counter. The available fan divisor

values are as follows:

The decimal count value can be calculated using the following equation:

Decimal count value = (1,200,000) / (RPM × divisor)

Any nominal RPM value can be used in the above equation with the

appropriate divisor as long as the maximum non-failure count value does not

exceed the limits of an 8-bit counter. Typical applications may consider 60% to

70% of nominal RPM a fan failure, which would result in a decimal count value

of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values.

FD1

FD0

Divisor

Nominal RPM

Decimal Count Value

8000

150 (96h)

4000

150 (96h)

2000

150 (96h)

1000

150 (96h)

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