P89V51RB2BBC datasheet(47/80 Pages) NXP

47 / 80 page

P89V51RB2_RC2_RD2_5

Product data sheet

Rev. 05 — 12 November 2009

47 of 80

NXP Semiconductors

P89V51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL

which allows the PCA to stop during Idle mode, WDTE which enables or disables the

Watchdog function on module 4, and ECF which when set causes an interrupt and the

PCA overﬂow ﬂag CF (in the CCON SFR) to be set when the PCA timer overﬂows.

The watchdog timer function is implemented in module 4 of PCA.

The CCON SFR contains the run control bit for the PCA (CR) and the ﬂags for the PCA

timer (CF) and each module (CCF4:0). To run the PCA the CR bit (CCON.6) must be set

by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the

PCA counter overﬂows and an interrupt will be generated if the ECF bit in the CMOD

set by hardware when either a match or a capture occurs. These ﬂags can only be cleared

by software. All the modules share one interrupt vector. The PCA interrupt system is

shown in Figure 22.

Each module in the PCA has a special function register associated with it. These registers

are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that

control the mode that each module will operate in.

The ECCF bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)

enables the CCFn ﬂag in the CCON SFR to generate an interrupt when a match or

compare occurs in the associated module (see Figure 22).

PWM (CCAPMn.1) enables the pulse width modulation mode.

The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to

toggle when there is a match between the PCA counter and the module’s

capture/compare register.

The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to

be set when there is a match between the PCA counter and the module’s

capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit

enables the positive edge. If both bits are set both edges will be enabled and a capture will

occur for either transition.

The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.

There are two additional registers associated with each of the PCA modules. They are

CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a

capture occurs or a compare should occur. When a module is used in the PWM mode

these registers are used to control the duty cycle of the output.

P89V51RB2BBC датащи(PDF) 47 Page - NXP Semiconductors