P89V51RB2BBC datasheet(39/80 Pages) NXP

39 / 80 page

P89V51RB2_RC2_RD2_5

Product data sheet

Rev. 05 — 12 November 2009

39 of 80

NXP Semiconductors

P89V51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

6.6.5 Framing error

Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0,

SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0

is set to ‘1’.

6.6.6 More about UART mode 1

Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is

sampled at a rate of 16 times whatever baud rate has been established. When a transition

is detected, the divide-by-16 counter is immediately reset to align its rollovers with the

boundaries of the incoming bit times.

The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th

counter states of each bit time, the bit detector samples the value of RXD. The value

accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise

rejection. If the value accepted during the ﬁrst bit time is not 0, the receive circuits are

reset and the unit goes back to looking for another 1-to-0 transition. This is to provide

rejection of false start bits. If the start bit proves valid, it is shifted into the input shift

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the

following conditions are met at the time the ﬁnal shift pulse is generated: (a) RI = 0, and

(b) either SM2 = 0, or the received stop bit = 1.

If either of these two conditions is not met, the received frame is irretrievably lost. If both

conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is

activated.

6.6.7 More about UART modes 2 and 3

Reception is performed in the same manner as in mode 1.

RB8

In modes 2 and 3, is the 9th data bit that was received. In mode 1, if

SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is

undeﬁned.

Transmit interrupt ﬂag. Set by hardware at the end of the 8th bit time in

mode 0, or at the stop bit in the other modes, in any serial

transmission. Must be cleared by software.

Receive interrupt ﬂag. Set by hardware at the end of the 8th bit time in

mode 0, or approximately halfway through the stop bit time in all other

modes. (See SM2 for exceptions). Must be cleared by software.

Table 27.

SCON - Serial port control register (address 98H) SM0/SM1 mode deﬁnition

SM0, SM1

UART mode

Baud rate

0 0

0: shift register

CPU clock / 6

0 1

1: 8-bit UART

variable

1 0

2: 9-bit UART

CPU clock / 32 or CPU clock / 16

1 1

3: 9-bit UART

variable

Table 26.

SCON - Serial port control register (address 98H) bit description …continued

Bit

Symbol

Description

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