LM8322 datasheet(11/42 Pages) NSC

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10.4 DEVICE CONFIGURATION AFTER RESET

After the LM8322 has completed its reset initialization, it will

have the following internal configuration:

•

PWM Clock — the PWM clock source is the on-chip clock

divided by 64. This remains in effect until changed by a

host command.

•

Keypad Size — 3 × 3.

•

Digital Multiplexers — disabled.

•

IRQ — enabled, active low.

•

NOINIT Bit — set.

•

Debounce Time — 3 scan cycles (about 12 milliseconds).

•

Active Time — 500 milliseconds.

10.5 CONFIGURATION INPUTS

The states sampled from the CONFIG_1 and CONFIG_2 in-

puts during reset select the ACCESS.bus address used by

the LM8322, as shown in Table 4. The address occupies the

high seven bits of the first byte of a bus transaction, with the

LSB (shown as X below) indicating the direction of transfer.

TABLE 4. Bus Address Selection

CONFIG_1

CONFIG_2

Bus Address

1000 010X

1000 011X

1000 100X

1000 101X

When these pins are used as GPIO ports, the design must

ensure that they have the desired states during reset. For ex-

ample, a 100-kohm resistor to ground can impose a logic 0

during reset without interfering with normal operation as a

GPIO port.

10.6 INITIALIZATION

The LM8322 waits for a WRITE_CFG command from the

host. During this time, IRQ is asserted to request service from

the host. Figure 3 describes the behavior of the LM8322 fol-

lowing reset.

30013603

FIGURE 3. LM8322 Initialization Behavior

Figure 4 shows the timing of IRQ relative to a RESET or POR

event and the WRITE_CFG command. 100 µs after a RE-

SET or POR event, IRQ is asserted and any READ_INT

command will return an interrupt code with the NOINIT bit set.

90 µs after a WRITE_CFG command is received, IRQ is de-

asserted.

30013604

FIGURE 4. IRQ Reset Timing

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