TAS5508C datasheet(3/107 Pages) TI

3 / 107 page

TAS5508C

www.ti.com

SLES257 – SEPTEMBER 2010

3.1.2

Error Status Register (0x02)

.................................................................................. 43

3.2

TAS5508C Pin Controls

.................................................................................................. 43

3.2.1

Reset (RESET)

................................................................................................. 43

3.2.2

Power Down (PDN)

............................................................................................ 45

3.2.3

Back-End Error (BKND_ERR)

................................................................................ 46

3.2.4

Speaker/Headphone Selector (HP_SEL)

.................................................................... 46

3.2.5

Mute (MUTE)

.................................................................................................... 46

3.3

Device Configuration Controls

........................................................................................... 47

3.3.1

Channel Configuration Registers

............................................................................. 47

3.3.2

Headphone Configuration Registers

......................................................................... 48

3.3.3

Audio System Configurations

................................................................................. 48

3.3.3.1

Using Line Outputs in 6-Channel Configurations

.............................................. 49

3.3.4

Recovery from Clock Error

.................................................................................... 49

3.3.5

Power-Supply Volume-Control Enable

....................................................................... 49

3.3.6

Volume and Mute Update Rate

............................................................................... 49

3.3.7

Modulation Index Limit

......................................................................................... 50

3.3.8

Interchannel Delay

.............................................................................................. 50

3.4

Master Clock and Serial Data Rate Controls

.......................................................................... 50

3.4.1

PLL Operation

................................................................................................... 51

3.5

Bank Controls

.............................................................................................................. 51

3.5.1

Manual Bank Selection

........................................................................................ 52

3.5.2

Automatic Bank Selection

..................................................................................... 52

3.5.2.1

Coefficient Write Operations While Automatic Bank Switch Is Enabled

.................... 52

3.5.3

Bank Set

......................................................................................................... 52

3.5.4

Bank-Switch Timeline

.......................................................................................... 52

3.5.5

Bank-Switching Example 1

.................................................................................... 53

3.5.6

Bank-Switching Example 2

.................................................................................... 53

Electrical Specifications

..................................................................................................... 55

4.1

Absolute Maximum Ratings

.............................................................................................. 55

4.2

Dissipation Rating Table (High-k Board, 105°C Junction)

........................................................... 55

4.3

Dynamic Performance At Recommended Operating Conditions at 25°C

.......................................... 55

4.4

Recommended Operating Conditions

.................................................................................. 55

4.5

Electrical Characteristics

................................................................................................. 56

4.6

PWM Operation

............................................................................................................ 56

4.7

Switching Characteristics

................................................................................................. 56

4.7.1

Clock Signals

.................................................................................................... 56

4.7.2

Serial Audio Port

................................................................................................ 57

4.7.3

2C Serial Control Port Operation

............................................................................. 58

4.7.4

Reset Timing (RESET)

......................................................................................... 59

4.7.5

Power-Down (PDN) Timing

................................................................................... 59

4.7.6

Back-End Error (BKND_ERR)

................................................................................ 60

4.7.7

Mute Timing (MUTE)

........................................................................................... 60

4.7.8

Headphone Select (HP_SEL)

................................................................................. 61

4.7.9

Volume Control

................................................................................................. 62

4.8

Serial Audio Interface Control and Timing

............................................................................. 62

4.8.1

2S Timing

....................................................................................................... 62

4.8.2

Left-Justified Timing

............................................................................................ 63

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