| поискавой системы для электроныых деталей |
|
TAS5508C датащи(PDF) 64 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TAS5508C датащи(HTML) 64 Page - Texas Instruments |
|
64 / 107 page ![]() 23 22 SCLK 32Clks LRCLK LeftChannel 24-BitMode 1 20-BitMode 16-BitMode 15 14 MSB LSB SCLK 32Clks RightChannel 2-ChannelRight-Justified(SonyFormat)StereoInput T0034-03 19 18 1 19 18 1 0 0 0 15 14 15 14 23 22 1 15 14 MSB LSB 19 18 1 19 18 1 0 0 0 15 14 15 14 TAS5508C SLES257 – SEPTEMBER 2010 www.ti.com 4.8.3 Right-Justified Timing Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508C masks unused leading data bit positions. Figure 4-11. Right-Justified 64-Fs Format 64 Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS5508C |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |