ATSAM3S datasheet(41/65 Pages) ATMEL

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6500AS–ATARM–11-Dec-09

SAM3S Summary

– Alarm register capable to generate a wake-up of the system through the Shut Down

Controller

10.10 Real Time Clock

• Low power consumption

• Full asynchronous design

• Two hundred year calendar

• Programmable Periodic Interrupt

• Alarm and update parallel load

• Control of alarm and update Time/Calendar Data In

10.11 General Purpose Backup Registers

• Eight 32-bit general-purpose backup registers

10.12 Nested Vectored Interrupt Controller

• Thirty maskable external interrupts

• Sixteen priority levels

• Processor state automatically saved on interrupt entry, and restored on

• Dynamic reprioritization of interrupts

• Priority grouping.

– selection of preempting interrupt levels and non-preempting interrupt levels.

• Support for tail-chaining and late arrival of interrupts.

– back-to-back interrupt processing without the overhead of state saving and

restoration between interrupts.

• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no

instruction overhead.

10.13 Chip Identification

• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.

• JTAG ID: 0x05B2D03F

Table 10-1.

SAM3S Chip IDs Register

Chip Name

Flash Size

(KBytes)

Pin Count

DBGU_CIDR

CHIPID_EXID

ATSAM3S4A (Rev A)

256

0x28800960

0x0

ATSAM3S2A (Rev A)

128

0x288A0760

0x0

ATSAM3S1A (Rev A)

0x28890560

0x0

ATSAM3S4B (Rev A)

256

0x28900960

0x0

ATSAM3S2B (Rev A)

128

0x289A0760

0x0

ATSAM3S1B (Rev A)

0x28990560

0x0

ATSAM3S4C (Rev A)

256

100

0x28A00960

0x0

ATSAM3S2C (Rev A)

128

100

0x28AA0760

0x0

ATSAM3S1C (Rev A)

100

0x28A90560

0x0

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