ATSAM3S datasheet(27/65 Pages) ATMEL

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6500AS–ATARM–11-Dec-09

SAM3S Summary

Processor and Architecture

7.1

ARM Cortex-M3 Processor

• Version 2.0

• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit

• Harvard processor architecture enabling simultaneous instruction fetch with data load/store

• Three-stage pipeline

• Single cycle 32-bit multiply

• Hardware divide

• Thumb and Debug states

• Handler and Thread modes

• Low latency ISR entry and exit

7.2

APB/AHB bridge

The SAM3S product embeds one peripheral bridge:

The peripherals of the bridge are clocked by MCK.

7.3

Matrix Masters

The Bus Matrix of the SAM3S product manages 4 masters, which means that each master can

perform an access concurrently with others, to an available slave.

Each master has its own decoder, which is defined specifically for each master. In order to sim-

plify the addressing, all the masters have the same decodings.

7.4

Matrix Slaves

The Bus Matrix of the SAM3S product manages 5 slaves. Each slave has its own arbiter, allow-

ing a different arbitration per slave.

Table 7-1.

List of Bus Matrix Masters

Master 0

Cortex-M3 Instruction/Data

Master 1

Cortex-M3 System

Master 2

Peripheral DMA Controller (PDC)

Master 3

CRC Calculation Unit

Table 7-2.

List of Bus Matrix Slaves

Slave 0

Internal SRAM

Slave 1

Internal ROM

Slave 2

Internal Flash

Slave 3

External Bus Interface

Slave 4

Peripheral Bridge

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