©2010 Silicon Storage Technology, Inc.

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1.8V Serial Quad I/O (SQI) Flash Memory

SST26WF032

Advance Information

To execute a Write-Suspend operation, the host drives CE# low, sends the Write Suspend command

cycle (B0H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. The Status

register indicates that the erase has been suspended by changing the WSE bit from ‘0’ to ‘1,’ but the

device will not accept another command until it is ready. To determine when the device will accept a

Write Suspend During Page Programming

Issuing a Write-Suspend instruction during Page Programming allows the host to erase or read any

sector that is not being programmed. Erase commands pointing to the suspended sector(s) will be

ignored. Any attempt to read from the suspended page will output unknown data because the program

will be incomplete.

To execute a Write Suspend operation, the host drives CE# low, sends the Write Suspend command

cycle (B0H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. The Status

register indicates that the programming has been suspended by changing the WSP bit from ‘0’ to ‘1,’

but the device will not accept another command until it is ready. To determine when the device will

Write-Resume

Write-Resume restarts a Write command that was suspended, and changes the suspend status bit in

the Status register (WSE or WSP) back to ‘0’.

To execute a Write-Resume operation, the host drives CE# low, sends the Write Resume command

cycle (30H), then drives CE# high. A cycle is two nibbles long, most significant nibble first. To deter-

mine if the internal, self-timed Write operation completed, poll the BUSY bit in the Status register, or

tively. The total write time before suspend and after resume will not exceed the uninterrupted write

Read Security ID

To execute a Read Security ID (SID) operation, the host drives CE# low, sends the Read Security ID

command cycle (88H), one address cycle, and then two dummy cycles. Each cycle is two nibbles long,

most significant nibble first.

After the dummy cycles, the device outputs data on the falling edge of the SCK signal, starting from the

specified address location. The data output stream is continuous through all SID addresses until termi-

nated by a low-to-high transition on CE#. The internal address pointer automatically increments until

the last SID address is reached, then outputs 00H until CE# goes high.

Figure 19:Read SID Sequence

Address

Dummy

Command

Data Byte 0

MSN

LSN

Data Byte 1 Data Byte 2

1409 F45.0

01

2

SCK

SIO[3:0]

CE#

C1

C0

A1

A0

X

H0

X

X

X

L0

H1

L1

H2

L2

78

11

10

913

12

MODE 3

MODE 0

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble