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33H датащи(PDF) 8 Page - Renesas Technology Corp |
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33H датащи(HTML) 8 Page - Renesas Technology Corp |
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8 / 54 page ![]() R8C/33G Group, R8C/33H Group 1. Overview Under development Preliminary document Specifications in this document are tentative and subject to change. REJ03B0306-0010 Rev.0.10 Page 8 of 51 Jul. 21, 2010 1.3 Block Diagram Figure 1.2 shows a Block Diagram. Figure 1.3 Block Diagram D/A converter (8 bits × 2) R8C CPU core System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator Memory ROM (1) RAM (2) Multiplier R0H R0L R1H R2 R3 R1L A0 A1 FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. 8 Port P1 6 Port P3 3 1 Port P4 8 Port P0 2 Port P5 Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) UART or clock synchronous serial I/O (8 bits × 2) SSU (8 bits × 1) Peripheral functions Watchdog timer (14 bits) A/D converter (10 bits × 12 channels) LIN module Comparator B Voltage detection circuit DTC Low-speed on-chip oscillator for watchdog timer |
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