SC668 datasheet(43/46 Pages) SEMTECH

43 / 46 page

SC668

ADP_RATE Bit D5

This bit sets the time that elapses before backlight current

reduces after ADP activates. A logic one delays reduction

of current for 4ms. A logic zero delays reduction of current

for 256µs.

When a reduction in bank #1 backlight current becomes

necessary, the first step change is delayed for 4ms (logic

one) or 256µs (logic zero). If bank #1 continues to need a

current reduction after the delay time has elapsed, the

brightness setting is lowered by one step. If further reduc-

tions in current are needed, the second and all subsequent

reductions occur at a faster rate equal to1/4 of the initial

delay time. Further reductions in current will stop when

the backlight accuracy and matching have normalized.

When 4ms is selected, the 1st delay = 4ms, and the 2nd and all

subsequent delays = 1ms. When 256μs is selected, the 1st

delay = 256μs, and the 2nd and all subsequent delays = 64μs.

ADP_EN Bit D4

This bit enables the ADP function. ADP is enabled when

this bit is a logic one. ADP is disabled when this bit is a

logic zero.

OLE_EN2 through OLE_EN0 Bits [D3:D1]

These bits enable Other Lighting Effects (OLE), including

the auto-dim full and auto-dim partial, as shown in Table

25. Auto-dim functions are described in detail in the

Applications Information section.

Table 25 — OLE Bits

OLE_EN2 OLE_EN1 OLE_EN0

Lighting Effect

Reserved (no effects)

Auto-dim full (group #1)

Auto-dim partial (group #1)

Reserved (no effects)

PWM_BYP Bit D0

When this bit is a logic zero, the PWM pin functions nor-

mally. When this bit is a logic one, the PWM pin is disabled,

so that a high or low on the PWM pin has no effect.

SC668 датащи(PDF) 43 Page - Semtech Corporation