SA9203/5

sames

7/14

FUNCTIONAL DESCRIPTION

The SA9203 contains the following:

•

Six 8-bit general purpose I/O ports programmable to be either byte or bit addressable.

•

Two control registers for configuring the device. These control registers can be read

back.

•

An internal address latch for accessing a multiplexed CPU address/data bus.

•

The SA9203 appears to the CPU as a peripheral device occupying 256 bytes of

memory space. Certain locations in the memory map are occupied by the six I/O

ports and two control registers.

The SA9203 supports two basic I/O port addressing modes, via; byte-addressing and

bit-addressing. Any of the six I/O ports can be configured as byte-addressable /or bit-

addressable. In bit-addressing, individual bits of any I/O port can be addressed

independently. In a bit- addressing CPU read operation, D0 contains valid data while

D1..D7 should be ignored. In a bit-addressing CPU write operation, D0 will be written

to the addressed output pin while D1..D7 will be ignored. The Address Memory map

is shown in Figure 5. The bit-addressing mode applies to both the I/O ports and the

control registers. The SA9205 is a three port device with operation is identical to the

SA9203.

FIGURE 5: Address Memory Map

WWWWWWWW

A7

A6

A5

A4

A3

A2

A1

A0

BM

EI

CR2 CR1 CR0 BM2 MB1 BM0

Bit mode address 0

Bit mode address 1

Bit mode address 2

Control register address 0

Control register address 1

Control register address 2

0: Interupt function disabled

1: Interupt function enabled

0: Bit mode addressing enabled

1: Byte mode addressing enabled