SA9203/5

sames

5/14

Pin

Type Designation

Description

18,52

VDD

+5V Supply Input

1,35

VSS

0V ground Reference

61..68

I/O

AD0..AD7

3-state address/data lines that interface with the CPU

lower 8-bit address/data bus. The 8-bit address is

latched into the SA9203 internal address latch on the

falling edge of ALE.

The 8-bit data is respectively

written into and read out of the SA9203 on WR and RD

signals.

2

N/C

Not connected.

3

I

CS

Active low input signal used to select the device.

4

I

ALE

This control signal latches the address on the AD0..7

lines on the falling edge of ALE.

5

I

RD

Input low on this line enables the data bus buffers.

6

I

WR

Input low on this line causes the data on the address/

data bus to be written to the I/O ports and, control

registers.

7

O

INT

If enabled via A.6, this output will be set (active edge

polarity programmed by D6 and output polarity

programmed via D7 of the Port B-F direction control

register) after data has been latched into PORT A.

8

I

RST

Input low on this line resets the chip and all internal

registers and all ports to input mode (The register

contents after a reset pulse will be described later).

9

I

STB

Input data on PORT A pins will be latched when STB is

active and transparent otherwise (polarity programmed

by D5 of the Port B-F direction control register)

10..17

I/O

PA0..PA7

8 general purpose I/O pins comprising PORT A. This

port supports individual input or latched output

configuration of each pin. In addition,each pin of PORT

A selected as an input can be programmed to be

latched or transparent.

19..26

I/O

PB0..PB7

8 general purpose I/O pins comprising PORT B. All 8

pins are programmed to be either latched outputs or

transparent inputs.

27..34

I/O

PC0..PC7

Identical to PORT B

36..43

I/O

PD0..PD7

Identical to PORT B

44..51

I/O

PE0..PE7

Identical to PORT B

53..60

I/O

PF0..PF7

Identical to PORT B

PIN DESCRIPTION for SA9203