SA2030

sames

7/12

PIN DESCRIPTION

Pin No. Name

Function

1

DB1

Bidirectional Alarm Port

2

DB2

Bidirectional Alarm Port

3

SP

Synchronisation Pulse output. Asserted during the bit interval immediately

prior to time-slot-zero of frames that contain FAS. Suppressed in the event

of frame-alignment loss.

4

R/W

Input for controlling direction of Alarm port data bus DB1 and DB2.

Internally pulled up to V

5

PE

Alarm port enable. Asserting this pin enables data transfers to or from

DB1 and DB2. Internally pulled up to V

6

RCL

Route Clock Input. 2.048 MHz clock that defines PCM input data timing.

The route clock is usually extracted from the route data.

7

SCL

System Clock Input.

2.048 MHz clock that defines the timing of the

terminating equipment.

8

BI

Buffer Inhibit Input. When true, the 1½ frame buffer is inhibited, and the

output frame timing is constrained to be within one-frame of the input

frame timing.

When false, the full 1½ frame buffer is enabled, and

immunity to wander is maximised. Buffer Inhibit Mode of operation is

intended for delay compensation between switching stages in one exhange

system. Internally pulled up to V

9

SCT

Station Clock Trigger input. Low going pulse used by the host system to

define the required output frame timing. SCT should be asserted on

alternate frames, during the data-bit interval immediately prior to time-

slot-zero. SCT input is enabled by asserting CE.

10

CE

Chip Enable input. When asserted the parallel outputs, B1 to B8 and P

are enabled. When CE = 1, parallel outputs are high impedance. CE must

also be asserted to enable the SCT input. Internally pulled-up to V

11

SO

Serial PCM Data Output. PCM-30 format output of aligned and retimed

data. Data clocked out under control of the System Clock SCL.

12

V

SS

Ground (0V) supply.

13

P

Parity Bit 3-state Ouput. Parity check for internal RAM. RAM data is saved

with Parity bit. Even Parity is used.

14

B1

3-State PCM Parallel Output (PCM sign bit).

15

B2

3-State PCM Parallel Output

16

B3

3-State PCM Parallel Output

17

B4

3-State PCM Parallel Output

18

B5

3-State PCM Parallel Output

19

B6

3-State PCM Parallel Output

20

B7

3-State PCM Parallel Output

21

B8

3-State PCM Parallel Output (LSB)

22

IN

PCM data input. Data is derived from route data and is clocked into the

circuit on rising edges of RCL.

23

FP

Fault Pulse Output. Fault pulses of 4 Route Clock cycles duration are

delivered whenever errors are detected in FAS, or on alternate frames in

the event of Frame Alignment loss.

24

V

DD

Supply Voltage (+5V Nominal)