SA2030

sames

9/12

Route Subsystem Timing

(At V

Characteristics

Sym

Min

Typ

Max

Unit

Test Conditions

Route Clock Period

T

RCL

400

488

600

ns

Note 1, 2, 3

Route Clock Duty Cycle

D

RCL

25

50

75

%

at 2,048MHz

Input Data Setup time

t

S

150

-

-

ns

Input Data Hold time

t

H

40

-

-

ns

Synch Pulse Width

t

SPW

-

488

-

ns

In Frame Synch

Synch Pulse Delay

t

DOSP

-

-

200

ns

In Frame Synch

Fault Pulse Width

t

FPW

-

1952

-

ns

After Bad FAS

Fault Pulse Delay

t

DOFP

-

-

200

ns

After Bad FAS

Synch Pulse Repeat Period

T

SP

-

250

-

µs

In Frame Synch

Fault Pulse Repeat Period

T

FP

-

250

-

µs

Out of Frame

Synch

Note: 1. The CCITT recommends clock frequency of 2,048MHz ±50ppm.

2. Incorrect Slip operation may occur if the Route clock and System clock differ by

more than 1% (10000ppm).

3. A Synch Alarm will be issued if the Route Clock frequency is less than 75% of the

Station Clock frequency.

Route Subsystem Timing Diagram