SC417_09 datasheet(20/30 Pages) SEMTECH

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SC417/SC427

LDO Regulator

The device features an integrated LDO regulator with a

programmable output voltage from 0.75V to 5.25V using

external resistors. The feedback pin (FBL) for the LDO is

regulated to 750mV. There is also an enable pin (ENL) for

the LDO that provides independent control. The LDO

voltage can also be used to provide the bias voltage for

the switching regulator.

VLDO

To FBL pin

RLDO2

RLDO1

Figure 9 — LDO Start-Up

The LDO output voltage is set by the following equation.

LDO

750

VLDO

A minimum capacitance of 1μF referenced to AGND is

normally required at the output of the LDO for stability. If

the LDO is providing bias power to the device, then a

minimum 0.1μF capacitor referenced to AGND is required

along with a minimum 1.0μF capacitor referenced to

PGND to filter the gate drive pulses. Refer to the layout

guidelines section.

LDO Start-up

Before start-up, the LDO checks the status of the following

signals to ensure proper operation can be maintained.

ENL pin

VLDO output

input voltage

When the ENL pin is high and V

is above the UVLO point,

the LDO will begin start-up. During the initial phase, when

the LDO output voltage is near zero, the LDO initiates a

current-limited start-up (typically 85mA) to charge the

output capacitor. When V

LDO

has reached 90% of the final

value (as sensed at the FBL pin), the LDO current limit is

increased to ~200mA and the LDO output is quickly driven

to the nominal value by the internal LDO regulator.

VVLDO Final

90% of VVLDO Final

Constant current startup

Voltage regulating with

~200mA current limit

Figure 10 — LDO Start-Up

LDO Switch-Over Operation

The SC417/SC427 includes a switch-over function for the

LDO. The switch-over function is designed to increase

efficiency by using the more efficient DC-DC converter to

power the LDO output, avoiding the less efficient LDO

regulator when possible. The switch-over function con-

nects the VLDO pin directly to the VOUT pin using an

internal switch. When the switch-over is complete the

LDO is turned off, which results in a power savings and

maximizes efficiency. If the LDO output is used to bias the

SC417/SC427, then after switch-over the device is self-

powered from the switching regulator with the LDO

turned off.

The switch-over logic waits for 32 switching cycles before

it starts the switch-over. There are two methods that

determine the switch-over of V

LDO

to V

OUT

In the first method, the LDO is already in regulation and

the DC-DC converter is later enabled. As soon as the

PGOOD output goes high, the 32 cycles are started. The

voltages at the VLDO and VOUT pins are then compared;

if the two voltages are within ±300mV of each other, the

VLDO pin connects to the VOUT pin using an internal

switch, and the LDO is turned off.

In the second method, the DC-DC converter is already

running and the LDO is enabled. In this case the 32 cycles

are started as soon as the LDO reaches 90% of its final

value. At this time, the VLDO and VOUT pins are compared,

and if within ±300mV the switch-over occurs and the LDO

is turned off.

Applications Information (continued)

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