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SC414EVB датащи(PDF) 23 Page - Semtech Corporation

номер детали SC414EVB
подробное описание детали  6A Integrated FET Regulator with 5V LDO
PDF  29 Pages
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производитель  SEMTECH [Semtech Corporation]
домашняя страница  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC414EVB датащи(HTML) 23 Page - Semtech Corporation

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SC414/SC424
23
Applications Information (continued)
L
T
)
V
V
(
I
ON
OUT
IN
RIPPLE
A
03
.
2
H
5
.
1
ns
311
)
V
1
8
.
10
(
I
VINMIN
_
RIPPLE
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is con-
trolled by the output ripple requirement and the DC toler-
ance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is for the output voltage regulation to be
±4% under static conditions. The internal 750mV refer-
ence tolerance is 1%. Assuming a 1% tolerance from the
FB resistor divider, this allows 2% tolerance due to V
OUT
ripple. Since this 2% error comes from 1/2 of the ripple
voltage, the allowable ripple is 4%, or 40mV for a 1V
output.
The maximum ripple current of 2.53A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
A
53
.
2
mV
40
I
V
ESR
RIPPLEMAX
RIPPLE
MAX
ESR
MAX = 15.8 mΩ
The output capacitance is chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor
current is at the peak, determines the required capaci-
tance. If the load release is instantaneous (load changes
from maximum to zero in < 1μs), the output capacitor
must absorb all the inductor’s stored energy. This will
cause a peak voltage on the capacitor according to the
following equation.
2
OUT
2
PEAK
2
RIPPLEMAX
OUT
MIN
V
V
I
2
1
I
L
COUT
Assuming a peak voltage V
PEAK
of 1.150 (100mV rise upon
load release), and a 6A load release, the required capaci-
tance is shown by the next equation.
2
2
2
MIN
V
1
V
05
.
1
A
53
.
2
2
1
A
6
H
5
.
1
COUT
COUT
MIN = 772μF
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-V
OUT
. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
The following can be used to calculate the needed capaci-
tance for a given dI
LOAD
/dt. Peak inductor current is shown
by the next equation.
I
LPK = IMAX + 1/2 x IRIPPLEMAX
I
LPK = 6A + 1/2 x 2.53A = 7.26A
dt
dl
Current
Load
of
change
of
Rate
LOAD
I
MAX = maximum load release = 6A
OUT
PK
LOAD
MAX
OUT
LPK
LPK
OUT
V
V
2
dt
dl
I
V
I
L
I
C
Example
s
1
A
25
.
1
dt
dl
LOAD



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