SC174 datasheet(18/27 Pages) SEMTECH

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Applications Information (continued)

and discharging during the switching cycle. For most ap-

plications, the total output ripple voltage is dominated

by the output capacitors, typically SP or POSCAP devices.

For stability the ESR zero of the output capacitor should

be lower than approximately one-third the switching fre-

quency. The formula for minimum ESR is shown by the

following equation.

Using Ceramic Output Capacitors

When applications use ceramic output capacitors, the

ESR is normally too small to meet the previously stated

ESR criteria. In these applications it is necessary to add

a small signal injection network as shown in Figure 9. In

this network R

L and CL filter the LX switching waveform to

generate an in-phase ripple voltage comparable to the

ripple seen on higher ESR capacitors. C

C is a coupling ca-

pacitor used to AC couple the generated ripple onto the

FB pin. Capacitor C

FF is required for min COUT applications.

This capacitor introduces a lead/lag into the control with

the maximum phase placed at 1/2 f

SW for added stability.

VLX

COUT

VIN

CFF

Figure 9 — Signal Injection Circuit

The values of R

L, CL, CC and CFF are dependent on the con-

ditions of the specific application such as V

IN, VOUT, fSW and

OUT. For switching frequencies ranging from 600kHz to

800kHz, calculations plus experimental test results show

that the following combination of R

L=2.5kW, CL=10nF,

C=68pF and CFF=39pF can be used for many output volt-

ages and loads.

OUT

MIN

ESR

Output Voltage Dropout

The output voltage adjustable range for continuous-

conduction operation is limited by the fixed 320ns (typi-

cal) minimum off-time. When working with low input

voltages, the duty-factor limit must be calculated using

worst-case values for on and off times. The duty-factor

limitation is shown by the next equation.

)

MAX

(

OFF

)

MIN

(

)

MIN

(

DUTY

The inductor resistance and MOSFET on-state voltage

drops must be included when performing worst-case

dropout duty-factor calculations.

System DC Accuracy — V

OUT Controller

Three factors affect V

OUT accuracy: the trip point of the FB

error comparator, the ripple voltage variation with line

and load, and the external resistor tolerance. The error

comparator offset is trimmed so that under static condi-

tions it trips when the feedback pin is 750mV, +1%.

The on-time pulse from the SC174 in the design example

is calculated to give a pseudo-fixed frequency of 800kHz.

Some frequency variation with line and load is expected.

This variation changes the output ripple voltage. Be-

cause adaptive on-time converters regulate to the valley

of the output ripple, ½ of the output ripple appears as a

DC regulation error. For example, if the output ripple is

50mV with V

IN = 5 volts, then the measured DC output

will be 25mV above the comparator trip point. If the rip-

ple increases to 30mV with V

IN = 5.5V, then the measured

DC output will be 15mV above the comparator trip. The

best way to minimize this effect is to minimize the output

ripple.

To compensate for valley regulation, it may be desirable

to use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of

trace resistance between the inductor and output ca-

pacitor. This trace resistance should be optimized so that

at full load the output droops to near the lower regula-

tion limit. Passive droop minimizes the required output

capacitance because the voltage excursions due to load

steps are reduced as seen at the load.

SC174

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