Preliminary
2-58
RF2119
Rev A8 010720
2
Pin
Function
Description
Interface Schematic
1GND
Ground externally.
2LMATCH
Interstage tuning. This pin is internally DC blocked and will connect to a
shunt inductor or microstrip line used for interstage tuning. Length from
pin to via should be approximately 60mils for 915MHz and 75mils for
902MHz and 120mils for 836MHz. The lumped element equivalent is
1.2nH to 2.0nH to ground, depending on frequency band of interest.
3GND
Ground externally.
4
VCC1
Power supply for stage 1. VCC should be fed through a 3.9nH inductor
with a decoupling capacitor on the VCC side.
5
GND1
Ground for stage 1. Keep traces physically short and connect immedi-
ately to ground plane for best performance.
6RF IN
RF input. An external DC blocking capacitor is required if this port is
connected to a DC path to ground or a DC voltage.
7GND
Ground externally.
8BIAS1
Ground return for the first stage bias. This pin should be connected to a
33nH inductor to ground.
9
VPC
Power control voltage. For maximum power, this voltage should be at
least 2.2V. To turn off, this voltage should be less than 0.6V. This pin
should be bypassed as close to the pin as practical.
10
NC
No connection.
11
NC
No connection.
12
RF OUT
RF output and power supply for the output stage. The bias for the out-
put stage is provided through this pin and pin 13. An external matching
network is required to provide the optimum load impedance; see the
application schematics for details.
13
RF OUT
Same as pin 12.
14
RF OUT
Same as pin 12.
15
NC
No connection.
16
BIAS2
Ground return for the second stage bias. This pin should be connected
to a 33nH inductor to ground.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
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