XIO2001IPNP datasheet(105/131 Pages) TI

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XIO2001

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SCPS212D – MAY 2009 – REVISED JANUARY 2010

6.4

GPIO Data Register

This register reads the state of the input mode GPIO terminals and changes the state of the output mode

GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The

secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL).

The default value at power up depends on the state of the GPIO terminals as they default to

general-purpose inputs. This register is an alias of the GPIO data register in the classic PCI configuration

space (offset B6h, see Section 4.60). See Table 6-3 for a complete description of the register contents.

Device control memory window register offset:

42h

Read-only, Read/Write

Default value:

00XXh

BIT NUMBER

RESET STATE

Table 6-3. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:5

RSVD

Reserved. Returns 000 0000 0000b when read.

4 (1)

GPIO4_Data

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state

of GPIO4 when in output mode.

3 (1)

GPIO3_Data

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state

of GPIO3 when in output mode.

2 (1)

GPIO2_Data

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state

of GPIO2 when in output mode.

1 (1)

GPIO1_Data

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state

of GPIO1 when in output mode.

0 (1)

GPIO0_Data

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state

of GPIO0 when in output mode.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Memory-Mapped TI Proprietary Register Space

105

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