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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001IPNP датащи(PDF) 51 Page - Texas Instruments |
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XIO2001IPNP датащи(HTML) 51 Page - Texas Instruments |
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51 / 131 page  XIO2001 www.ti.com SCPS212D – MAY 2009 – REVISED JANUARY 2010 4.18 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4-9 for a complete description of the register contents. PCI register offset: 20h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-9. Memory Base Register Description BIT FIELD NAME ACCESS DESCRIPTION Memory base. Defines the lowest address of the memory address range that determines when to 15:4 MEMBASE RW forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h. 3:0 RSVD R Reserved. Returns 0h when read. 4.19 Memory Limit Register This read/write register specifies the upper limit of the memory addresses that the bridge forwards downstream. See Table 4-10 for a complete description of the register contents. PCI register offset: 22h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-10. Memory Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION Memory limit. Defines the highest address of the memory address range that determines when to 15:4 MEMLIMIT RW forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh. 3:0 RSVD R Reserved. Returns 0h when read. 4.20 Prefetchable Memory Base Register This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards downstream. See Table 4-11 for a complete description of the register contents. PCI register offset: 24h Register type: Read-only, Read/Write Default value: 0001h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Copyright © 2009–2010, Texas Instruments Incorporated Classic PCI Configuration Space 51 Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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