XIO2001IPNP datasheet(81/131 Pages) TI

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XIO2001

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SCPS212D – MAY 2009 – REVISED JANUARY 2010

4.69 Arbiter Control Register

The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier

rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority

arbitration tier. See Table 4-43 for a complete description of the register contents.

PCI register offset:

DCh

Read/Write

Default value:

40h

BIT NUMBER

RESET STATE

Table 4-43. Clock Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7(1)

Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.

When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is

cleared, the arbiter parks the bus on the last device mastering the secondary bus.

PARK

0 = Park the secondary bus on the last secondary bus master (default)

1 = Park the secondary bus on the bridge

6 (1)

Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration

scheme.

BRIDGE_TIER_SEL

0 = Lowest priority tier

1 = Highest priority tier (default)

5(1)

GNT5 tier select. This bit determines in which tier GNT5 is placed in the arbitration

scheme.

TIER_SEL5