FS6377 datasheet(18/24 Pages) ONSEMI

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FS6377

Table 13: AC Timing Specifications

Parameter

Symbol

Conditions/Descriptions

Clock

(MHz)

Min.

Typ.

Max.

Units

Overall

Output frequency*

VDD = 5.5V

VDD = 3.6V

0.8

150

100

MHz

VCO frequency*

fVCO

VDD = 5.5V

VDD = 3.6V

230

170

MHz

VCO gain*

AVCO

400

MHz/V

Loop filter time constant*

LFTC bit = 0

LFTC bit = 1

µs

Rise time*

VO = 0.5V to 4.5V; CL = 15pF

VO = 0.3V to 3.0V; CL = 15pF

1.9

1.6

Fall time*

VO = 4.5V to 0.5V; CL = 15pF

VO = 3.0V to 0.3V; CL = 15pF

1.8

1.5

Tristate enable delay*

tPZL, tPZH

Tristate disable delay*

tPZL, tPZH

Clock stabilization time*

tSTB

Output active from power-up, via PD pin

After last register is written

100

µs

Divider Modulus

Feedback divider

See Table 2

2047

Reference divider

255

Post divider

See Table 8

Clock Outputs (PLL A clock via CLK_A pin) Approximate

Duty cycle*

Ratio of pulse width (as measured from rising edge

to next falling edge at 2.5V) to one clock period

100

Jitter, long term (

σy(τ))*

tj(LT)

On rising edges 500µs apart at 2.5V relative to an

ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,

NR = 63, NPX = 50, no other PLLs active

On rising edges 500µs apart at 2.5V relative to an

ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,

NR = 63, NPX = 50, all other PLLs active (B = 60MHz,

C = 40MHz, D = 14.318MHz)

100

165

Jitter, period (peak-peak)*

tj(ΔP)

From rising edge to the next rising edge at 2.5V,

CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,

NPX = 50, no other PLLs active

From rising edge to the next rising edge at 2.5V,

CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,

NPX = 50, all other PLLs active (B = 60MHz,

C = 40MHz, D = 14.318MHz)

100

110

390

Clock Outputs (PLL B clock via CLK_B pin) Approximate

Duty cycle*

Ratio of pulse width (as measured from rising edge

to next falling edge at 2.5V) to one clock period

100

Jitter, long term (

σy(τ))*

tj(LT)

On rising edges 500µs apart at 2.5V relative to an

ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,

NR = 63, NPX = 50, no other PLLs active

On rising edges 500µs apart at 2.5V relative to an

ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,

NR = 63, NPX = 50, all other PLLs active (A = 50MHz,

C = 40MHz, D = 14.318MHz)

100

Jitter, period (peak-peak)*

tj(ΔP)

From rising edge to the next rising edge at 2.5V,

CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,

NPX = 50, no other PLLs active

From rising edge to the next rising edge at 2.5V,

CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,

NPX = 50, all other PLLs active (A = 50MHz,

C = 40MHz, D = 14.318MHz)

100

120

400

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