SC312XDP512F0MPVR datasheet(122/1348 Pages) FREESCALE

122 / 1348 page

Chapter 3 Pierce Oscillator (S12XOSCLCPV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

122

Freescale Semiconductor

3.2.3

XCLKS — Input Signal

The XCLKS is an input signal which controls whether a crystal in combination with the internal loop

controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock

circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS

pin. Table 3-1 lists the state coding of the sampled XCLKS signal.

3.3

Memory Map and Register Deﬁnition

The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.

3.4

Functional Description

The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal

level which is determined by the amount of hysteresis being used and the maximum oscillation range.

The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is

intended to be connected to either a crystal or an external clock source. The selection of loop controlled

Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is

sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback.

A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is

3.4.1

Gain Control

A closed loop control system will be utilized whereby the ampliﬁer is modulated to keep the output

waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be kept

above twice the maximum hysteresis level of the input buffer. Electrical speciﬁcation details are provided

in the Electrical Characteristics appendix.

3.4.2

Clock Monitor

The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU

clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure

which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock

monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function

is enabled/disabled by the CME control bit, described in the CRG block description chapter.

Table 3-1. Clock Selection Based on XCLKS

XCLKS

Description

Loop controlled Pierce oscillator selected

Full swing Pierce oscillator/external clock selected

SC312XDP512F0MPVR датащи(PDF) 122 Page - Freescale Semiconductor, Inc