SC312XDP512F0MPVR datasheet(109/1348 Pages) FREESCALE

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Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

109

2.4.3.3.1

Wake-up from Pseudo Stop Mode (PSTP=1)

Wake-up from pseudo stop mode is the same as wake-up from wait mode. There are also four different

scenarios for the CRG to restart the MCU from pseudo stop mode:

•

External reset

•

Clock monitor fail

•

COP reset

•

Wake-up interrupt

If the MCU gets an external reset or COP reset during pseudo stop mode active, the CRG asynchronously

restores all conﬁguration bits in the register space to its default settings and starts the reset generator. After

completing the reset sequence processing begins by fetching the normal or COP reset vector. pseudo stop

mode is left and the MCU is in run mode again.

If the clock monitor is enabled (CME = 1), the MCU is able to leave pseudo stop mode when loss of

oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG

generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same

compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the

SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the

interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 2.4.1.4, “Clock

Quality Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by

SCMIE=0, the SCMIF ﬂag will be asserted but the CRG will not wake-up from pseudo stop mode.

If any other interrupt source (e.g., RTI) triggers exit from pseudo stop mode, the MCU immediately

continues with normal operation. Because the PLL has been powered-down during stop mode, the

PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the

PLLSEL bit again, in order to switch system and core clocks to the PLLCLK.

Table 2-13 summarizes the outcome of a clock loss while in pseudo stop mode.

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