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SC312XDP512F0MPVR датащи(PDF) 1020 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 1020 Page - Freescale Semiconductor, Inc |
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1020 / 1348 page ![]() Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 1022 Freescale Semiconductor 24.0.5.53 Port J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. 24.0.5.54 Port J Pull Device Enable Register (PERJ) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. 76543210 R RDRJ7 RDRJ6 0000 RDRJ1 RDRJ0 W Reset 00000000 = Unimplemented or Reserved Figure 24-55. Port J Reduced Drive Register (RDRJ) Table 24-49. RDRJ Field Descriptions Field Description 7–0 RDRJ[7:6] RDRJ[1:0] Reduced Drive Port J 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 76543210 R PERJ7 PERJ6 0000 PERJ1 PERJ0 W Reset 11000011 = Unimplemented or Reserved Figure 24-56. Port J Pull Device Enable Register (PERJ) |
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