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SC312XDP512F0MPVR датащи(PDF) 1013 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 1013 Page - Freescale Semiconductor, Inc |
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1013 / 1348 page ![]() 24.0.5.40 Port P Interrupt Enable Register (PIEP) Read: Anytime. Write: Anytime. This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P. 24.0.5.41 Port P Interrupt Flag Register (PIFP) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the corresponding bit in the PIFP register. Writing a “0” has no effect. Table 24-38. PPSP Field Descriptions Field Description 7–0 PPSP[7:0] Polarity Select Port P 0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 76543210 R PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W Reset 00000000 Figure 24-42. Port P Interrupt Enable Register (PIEP) Table 24-39. PIEP Field Descriptions Field Description 7–0 PIEP[7:0] Interrupt Enable Port P 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 76543210 R PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W Reset 00000000 Figure 24-43. Port P Interrupt Flag Register (PIFP) |
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